To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
38B7
Group
User's Manual
http://www.infomicom.maec.co.jp/indexe.htm
Before using this material, please visit the above website to confirm that this is the most current document available.
Rev. 1.3 Revision date: Jan. 29, 2003
Keep safety first in your circuit designs!
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Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http:// www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
REVISION HISTORY
Rev. 1.0 1.1 Date Page 07/07/00 03/10/00 74 100 First Edition
38B7 GROUP USER'S MANUAL
Description Summary
Mask options B to G are shaded to show that they cannoto be specified. Note 4 added. Absolute maximum ratings VEE VCC-45 to VCC +0.3 VI VCC-45 to VCC +0.3 VO VCC-45 to VCC +0.3 Explanations of "DESCRIPTION" are partly eliminated. Oscillation frequency value of "FEATURES" are partly revised. Figure 3 is partly revised. Figure 4 is partly revised. "MASK OPTION OF PULL-DOWN RESISTOR" is eliminated. Explanations of "sNote" are revised. "sNotes" is added. "Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs" is added. Sub clause name and explanations of "(7) Setting procedure when serial I/O2 transmit interrupt is used" are revised. Clause name and explanations of "2.11.3 Each port state during "L" state of RESET pin" are revised. Table name of Table 2.11.1 is revised. Note of Table 2.11.1 is eliminated. Table 2.13.1 is partly revised. Explanations of "2.13.5 Serial I/O mode" are partly revised. Table 2.13.2 is partly revised. Figure 3.2.2 is revised. Sub clause name and explanations of "(1) Change of relevant register settings" are revised. Sub clause name and explanations of "(7) Setting procedure when serial I/O2 transmit interrupt is used" are revised. Clause name and explanations of "3.3.11 Each port state during "L" state of RESET pin" are revised. Table name of Table 3.3.3 is revised.
1.2
11/01/01
1-2 1-2 1-7 1-8 1-75 1-21 1-41 1-100 2-91 2-164 2-164 2-164 2-177 2-177 2-177 3-10 3-15 3-21 3-23 3-23
1.3
01/29/03
(1/1)
Preface
This user's manual describes Mitsubishi's CMOS 8bit microcomputers 38B7 Group. After reading this manual, the user should have a through knowledge of the functions and features of the 38B7 Group, and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. For details of software, refer to the "740 Family Software Manual." For details of development support tools, refer to the "Mitsubishi Microcomputer Development Support Tools" Homepage (http://www.tool-spt.maec.co.jp/index_e.htm).
BEFORE USING THIS USER'S MANUAL
This user's manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development.
1. Organization
q CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. q CHAPTER 3 APPENDIX This chapter includes a list of registers, and necessary information for systems development using the microcomputer.
2. Structure of Register
The figure of each register structure describes its functions, contents at reset, and attributes as follows:
(Note 2)
Bits
b7 b6 b5 b4 b3 b2 b1 b0 0
Bit attributes
(Note 1)
Contents immediately after reset release
CPU mode register (CPUM) [Address : 3B 16] b 0 1 2 3 4 5 6 7 Stack page selection bit Name Processor mode bits
b1 b0
Functions
0 0 : Single-chip mode 01: 1 0 : Not available 11: 0 : 0 page 1 : 1 page
At reset
RW
0 0 0 0 0 0
Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0." Fix this bit to "0." Main clock division ratio selection bits
0 0 : = XIN/2 (High-speed mode) 0 1 : = XIN/8 (Middle-speed mode) 1 0 : = XIN/8 (Middle-speed mode) 1 1 : = XIN (Double-speed mode)
b7 b6
1 0
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Notes 1: Contents immediately after reset release 0******"0" at reset release 1******"1" at reset release Undefined******Undefined or reset release ******Contents determined by option at reset release 2: Bit attributes******The attributes of control register bits are classified into 3 bytes : read-only, write-only and read and write. In the figure, these attributes are represented as follows : R******Read ******Read enabled ******Read disabled W******Write ******Write enabled ******Write disabled
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2 FEATURES .................................................................................................................................... 1-2 APPLICATION ................................................................................................................................ 1-2 PIN CONFIGURATION .................................................................................................................. 1-3 FUNCTIONAL BLOCK .................................................................................................................. 1-4 PIN DESCRIPTION ........................................................................................................................ 1-5 PART NUMBERING ....................................................................................................................... 1-7 GROUP EXPANSION .................................................................................................................... 1-8 Memory Type ............................................................................................................................ 1-8 Memory Size ............................................................................................................................. 1-8 Package ..................................................................................................................................... 1-8 FUNCTIONAL DESCRIPTION ...................................................................................................... 1-9 Central Processing Unit (CPU) .............................................................................................. 1-9 Memory .................................................................................................................................... 1-13 I/O Ports .................................................................................................................................. 1-15 Interrupts ................................................................................................................................. 1-21 Timers ...................................................................................................................................... 1-24 Serial I/O ................................................................................................................................. 1-29 FLD Controller ........................................................................................................................ 1-44 A-D Converter ......................................................................................................................... 1-61 D-A Converter ......................................................................................................................... 1-62 PWM (Pulse Width Modulation) ........................................................................................... 1-63 Interrupt Interval Determination Function ............................................................................ 1-66 Watchdog Timer ..................................................................................................................... 1-68 Buzzer Output Circucit .......................................................................................................... 1-69 Reset Circuit ........................................................................................................................... 1-70 Clock Generating Circuit ....................................................................................................... 1-72 Power Dissipation Calculating Method ................................................................................ 1-75 Flash Memory Mode .............................................................................................................. 1-78 NOTES ON PROGRAMMING ..................................................................................................... 1-99 NOTES ON USAGE ................................................................................................................... 1-100 DATA REQUIRED FOR MASK ORDERS .............................................................................. 1-100
CHAPTER 2 APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2 2.1.1 Memory assignment ....................................................................................................... 2-2 2.1.2 Relevant registers .......................................................................................................... 2-3 2.1.3 Terminate unused pins .................................................................................................. 2-8 2.1.4 Notes on I/O port ........................................................................................................... 2-9 2.1.5 Termination of unused pins ........................................................................................ 2-10 2.2 Timer ....................................................................................................................................... 2-11 2.2.1 Memory map ................................................................................................................. 2-10 2.2.2 Relevant registers ........................................................................................................ 2-12 2.2.3 Timer application examples ........................................................................................ 2-21
38B7 Group User's Manual
i
Table of contents
2.3 Serial I/O ................................................................................................................................ 2-37 2.3.1 Memory map ................................................................................................................. 2-37 2.3.2 Relevant registers ........................................................................................................ 2-38 2.3.3 Serial I/O1 connection examples ............................................................................... 2-50 2.3.4 Serial I/O1's modes ..................................................................................................... 2-52 2.3.5 Serial I/O1 application examples ............................................................................... 2-53 2.3.6 Serial I/O2 connection examples ............................................................................... 2-59 2.3.7 Serial I/O2's modes ..................................................................................................... 2-61 2.3.8 Serial I/O2 application examples ............................................................................... 2-62 2.3.9 Serial I/O3 connection examples ............................................................................... 2-81 2.3.10 Serial I/O3's modes ................................................................................................... 2-83 2.3.11 Serial I/O3 application examples ............................................................................. 2-84 2.3.12 Notes on serial I/O1 .................................................................................................. 2-87 2.3.13 Notes on serial I/O2 .................................................................................................. 2-89 2.4 FLD controller ...................................................................................................................... 2-92 2.4.1 Memory assignment ..................................................................................................... 2-92 2.4.2 Relevant registers ........................................................................................................ 2-93 2.4.3 FLD controller application examples ....................................................................... 2-101 2.4.4 Notes on FLD controller ............................................................................................ 2-132 2.5 A-D converter ..................................................................................................................... 2-133 2.5.1 Memory assignment ................................................................................................... 2-133 2.5.2 Relevant registers ...................................................................................................... 2-134 2.5.3 A-D converter application examples ........................................................................ 2-138 2.5.4 Notes on A-D converter ............................................................................................ 2-140 2.6 D-A converter ..................................................................................................................... 2-141 2.6.1 Memory assignment ................................................................................................... 2-141 2.6.2 Relevant registers ...................................................................................................... 2-141 2.6.3 D-A converter application examples ........................................................................ 2-143 2.6.4 Notes on D-A converter ............................................................................................ 2-144 2.7 PWM ...................................................................................................................................... 2-145 2.7.1 Memory assignment ................................................................................................... 2-145 2.7.2 Relevant registers ...................................................................................................... 2-145 2.7.3 PWM application example ......................................................................................... 2-147 2.7.4 Notes on PWM ........................................................................................................... 2-148 2.8 Interrupt interval determination function ..................................................................... 2-149 2.8.1 Memory assignment ................................................................................................... 2-149 2.8.2 Relevant registers ...................................................................................................... 2-149 2.8.3 Interrupt interval determination function application examples ............................ 2-153 2.9 Watchdog timer .................................................................................................................. 2-157 2.9.1 Memory assignment ................................................................................................... 2-157 2.9.2 Relevant register ........................................................................................................ 2-157 2.9.3 Watchdog timer application examples ..................................................................... 2-159 2.9.4 Notes on watchdog timer .......................................................................................... 2-160 2.10 Buzzer output circuit ...................................................................................................... 2-161 2.10.1 Memory assignment ................................................................................................. 2-161 2.10.2 Relevant register ...................................................................................................... 2-161 2.10.3 Buzzer output circuit application examples .......................................................... 2-162 2.11 Reset circuit ..................................................................................................................... 2-163 2.11.1 Connection example of reset IC ............................................................................ 2-163 2.11.2 Notes on reset .......................................................................................................... 2-164 2.11.3 Each port state during "L" state of RESET pin ................................................... 2-164
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Table of contents
2.12 Clock generating circuit ................................................................................................ 2-165 2.12.1 Relevant register ...................................................................................................... 2-165 2.12.2 Clock generating circuit application examples ..................................................... 2-166 2.13 Flash memory ................................................................................................................... 2-174 2.13.1 Overview .................................................................................................................... 2-174 2.13.2 Memory map ............................................................................................................. 2-174 2.13.3 Relevant registers .................................................................................................... 2-175 2.13.4 Parallel I/O mode ..................................................................................................... 2-177 2.13.5 Serial I/O mode ........................................................................................................ 2-177 2.13.6 CPU reprogramming mode ..................................................................................... 2-178 2.13.7 Flash memory mode application examples .......................................................... 2-179 2.13.8 Notes on CPU reprogramming mode .................................................................... 2-188 2.13.9 Notes on flash memory version ............................................................................. 2-188
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2 3.1.1 Absolute maximum ratings ............................................................................................ 3-2 3.1.2 Recommended operating conditions ............................................................................ 3-2 3.1.3 Electrical characteristics ................................................................................................ 3-4 3.1.4 A-D converter characteristics ....................................................................................... 3-6 3.1.5 D-A converter characteristics ....................................................................................... 3-6 3.1.6 Timing requirements and switching characteristics ................................................... 3-7 3.2 Standard characteristics .................................................................................................... 3-10 3.2.1 Power source current standard characteristics ........................................................ 3-10 3.2.2 Port standard characteristics ...................................................................................... 3-11 3.2.3 A-D conversion standard characteristics ................................................................... 3-14 3.3 Notes on use ........................................................................................................................ 3-15 3.3.1 Notes on interrupts ...................................................................................................... 3-15 3.3.2 Notes on I/O port ......................................................................................................... 3-16 3.3.3 Notes on serial I/O1 .................................................................................................... 3-17 3.3.4 Notes on serial I/O2 .................................................................................................... 3-19 3.3.5 Notes on FLD controller .............................................................................................. 3-21 3.3.6 Notes on A-D converter .............................................................................................. 3-22 3.3.7 Notes on D-A converter .............................................................................................. 3-22 3.3.8 Notes on PWM ............................................................................................................. 3-22 3.3.9 Notes on watchdog timer ............................................................................................ 3-23 3.3.10 Notes on reset ............................................................................................................ 3-23 3.3.11 Each pin state during "L" state of RESET pin ...................................................... 3-23 3.3.12 Notes on programming .............................................................................................. 3-24 3.3.13 Notes on CPU reprogramming mode ...................................................................... 3-26 3.3.14 Notes on flash memory version ............................................................................... 3-26 3.3.15 Termination of unused pins ...................................................................................... 3-27 3.4 Countermeasures against noise ...................................................................................... 3-28 3.4.1 Shortest wiring length .................................................................................................. 3-28 3.4.2 Connection of bypass capacitor across VSS line and VCC line ............................... 3-30 3.4.3 Wiring to analog input pins ........................................................................................ 3-31 3.4.4 Oscillator concerns ....................................................................................................... 3-32 3.4.5 Setup for I/O ports ....................................................................................................... 3-33 3.4.6 Providing of watchdog timer function by software .................................................. 3-34
38B7 Group User's Manual
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Table of contents
3.5 Control registers .................................................................................................................. 3-35 3.6 Package outline ................................................................................................................... 3-75 3.7 Machine instructions .......................................................................................................... 3-76 3.8 List of instruction code ..................................................................................................... 3-87 3.9 M35501FP .............................................................................................................................. 3-88 3.10 SFR memory map ............................................................................................................ 3-100 3.11 Pin configuration ............................................................................................................. 3-101
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38B7 Group User's Manual
List of figures
List of figures
CHAPTER 1 HARDWARE
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 Pin configuration of M38B79MFH-XXXXFP .................................................................... 1-3 2 Functional block diagram ................................................................................................... 1-4 3 Part numbering .................................................................................................................... 1-7 4 Memory expansion plan ..................................................................................................... 1-8 5 740 Family CPU register structure................................................................................... 1-9 6 Register push and pop at interrupt generation and subroutine call ......................... 1-10 7 Structure of CPU mode register ..................................................................................... 1-12 8 Memory map diagram ...................................................................................................... 1-13 9 Memory map of special function register (SFR) .......................................................... 1-14 10 Structure of pull-up control registers (PULL1, PULL2 and PULL3) ........................ 1-15 11 Port block diagram (1) ................................................................................................... 1-18 12 Port block diagram (2) ................................................................................................... 1-19 13 Port block diagram (3) ................................................................................................... 1-20 14 Interrupt control ............................................................................................................... 1-23 15 Structure of interrupt related registers ........................................................................ 1-23 16 Structure of timer related register ................................................................................ 1-24 17 Block diagram of timer .................................................................................................. 1-25 18 Timing chart of timer 6 PWM1 mode ........................................................................... 1-26 19 Block diagram of timer X .............................................................................................. 1-28 20 Structure of timer X related registers .......................................................................... 1-28 21 Block diagram of serial I/O1 ......................................................................................... 1-29 22 Structure of serail I/O1 control registers 1, 2 ............................................................ 1-30 23 Structure of serial I/O1 control register 3 ................................................................... 1-31 24 Structure of serial I/O1 automatic transfer data pointer ........................................... 1-32 25 Automatic transfer serial I/O operation ....................................................................... 1-33 26 SSTB1 output operation .................................................................................................... 1-34 27 SBUSY1 input operation (internal synchronous clock) ................................................... 1-34 28 SBUSY1 input operation (external synchronous clock) .................................................. 1-34 29 SBUSY1 output operation (internal synchronous clock, 8-bits serial I/O) ................... 1-35 30 SBUSY1 output operation (external synchronous clock, 8-bits serial I/O) .................. 1-35 31 SBUSY1 output operation in automatic transfer serial I/O mode (internal synchronous clock, SBUSY1 output function outputs each 1-byte) ................................................... 1-35 32 SRDY1 output operation .................................................................................................... 1-36 33 SRDY1 input operation (internal synchronous clock) .................................................... 1-36 34 Handshake operation at serial I/O1 mutual connecting (1) ...................................... 1-37 35 Handshake operation at serial I/O1 mutual connecting (2) ...................................... 1-37 36 Block diagram of clock snchronous serial I/O2 ......................................................... 1-38 37 Operation of clock synchronous serial I/O2 function ................................................ 1-38 38 Block diagram of UART serial I/O2 ............................................................................. 1-39 39 Operation of UART serial I/O2 function ...................................................................... 1-39 40 Structure of serial I/O2 related register ...................................................................... 1-41 41 Block diagram of serial I/O3 ......................................................................................... 1-42 42 Structure of serial I/O3 control register ....................................................................... 1-42 43 Timing of serial I/O3 (LSB first) ................................................................................... 1-43 44 Block diagram for FLD control circuit .......................................................................... 1-45 45 Structure of FLDC related registers (1) ...................................................................... 1-46 46 Structure of FLDC related registers (2) ...................................................................... 1-47
38B7 Group User's Manual
i
List of figures
Fig. 47 Structure of FLDC related registers (3) ...................................................................... 1-48 Fig. 48 Structure of FLDC related registers (4) ...................................................................... 1-49 Fig. 49 Segment/Digit setting example ..................................................................................... 1-50 Fig. 50 FLD automatic display RAM assignment .................................................................... 1-51 Fig. 51 Example of using FLD automatic display RAM in 16-timing*ordinary mode ......... 1-52 Fig. 52 Example of using FLD automatic display RAM in 16-timing*gradation display mode ........................................................................................................................................................ 1-53 Fig. 53 Example of using FLD automatic display RAM in 32-timing mode ......................... 1-54 Fig. 54 FLD and digit output timing .......................................................................................... 1-55 Fig. 55 Timing using digit interrupt ........................................................................................... 1-56 Fig. 56 Timing using FLD blanking interrupt ............................................................................ 1-57 Fig. 57 P64 to P67 FLD output pulses ...................................................................................... 1-58 Fig. 58 Toff section generating/nothing function ..................................................................... 1-59 Fig. 59 Digit pulses output function .......................................................................................... 1-60 Fig. 60 Structure of AD/DA control register ............................................................................. 1-61 Fig. 61 Black diagram of A-D converter ................................................................................... 1-61 Fig. 62 Black diagram of D-A converter ................................................................................... 1-62 Fig. 63 Equivalent connection circuit of D-A converter .......................................................... 1-62 Fig. 64 PWM block diagram ....................................................................................................... 1-63 Fig. 65 PWM timing ..................................................................................................................... 1-64 Fig. 66 Structure of PWM control register ............................................................................... 1-65 Fig. 67 14-bit PWM timing .......................................................................................................... 1-65 Fig. 68 Interrupt interval determination circuit block diagram ............................................... 1-66 Fig. 69 Structure of itnerrupt interval determination control register .................................... 1-67 Fig. 70 Interrupt inteval determination operation example (at rising edge active) ............. 1-67 Fig. 71 Interrupt interval determination operation example (at both-sided edge active) ... 1-67 Fig. 72 Block diagram of watchdog timer ................................................................................. 1-68 Fig. 73 Structure of watchdog timer control register .............................................................. 1-68 Fig. 74 Block diagram of buzzer output circuit ........................................................................ 1-69 Fig. 75 Structure of buzzer output control register ................................................................ 1-69 Fig. 76 Reset circuit example .................................................................................................... 1-70 Fig. 77 Reset sequence .............................................................................................................. 1-70 Fig. 78 Internal status at reset .................................................................................................. 1-71 Fig. 79 Ceramic resonator circuit .............................................................................................. 1-72 Fig. 80 External clock input circuit ............................................................................................ 1-72 Fig. 81 Clock generating circuit block diagram ....................................................................... 1-73 Fig. 82 State transitions of system clock ................................................................................. 1-74 Fig. 83 Digit timing waveform (1) .............................................................................................. 1-76 Fig. 84 Digit timing waveform (2) .............................................................................................. 1-77 Fig. 85 Pin connection of M38B79FF when operating in parallel input/output mode ........ 1-80 Fig. 86 Read timong .................................................................................................................... 1-81 Fig. 87 Timings during reading .................................................................................................. 1-82 Fig. 88 Input/output timings during programming (Verify data is output at the same timing as for read.) ......................................................................................................................... 1-83 Fig. 89 Input/output timings during erasing (verify data is output at the same timing as for read.)................................................................................................................................ 1-84 Fig. 90 Programming/Erasing algorithm flow chart ................................................................. 1-86 Fig. 91 Pin connection of M38B79FF when operating in serial I/O mode .......................... 1-88 Fig. 92 Timings during reading .................................................................................................. 1-90 Fig. 93 Timings during programming ......................................................................................... 1-91 Fig. 94 Timings during program verify ...................................................................................... 1-91 Fig. 95 Timings at erasing .......................................................................................................... 1-92
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38B7 Group User's Manual
List of figures
Fig. Fig. Fig. Fig. Fig. Fig. 96 Timings during erase verify........................................................................................... 1-92 97 Timings at error checking .............................................................................................. 1-93 98 Flash memory control register bit configuration ......................................................... 1-95 99 Flash command register bit configuration ................................................................... 1-96 100 CPU mode register bit configuration in CPU rewriting mode ................................ 1-96 101 Flowchart of program/erase operation at CPU reprogramming mode .................. 1-98
CHAPTER 2 APPLICATION
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 Memory assignment of I/O port relevant registers .................................................. 2-2 2.1.2 Structure of port Pi (i = 0 to 7, 9, A) ....................................................................... 2-3 2.1.3 Structure of port P8 ..................................................................................................... 2-3 2.1.4 Structure of port PB..................................................................................................... 2-4 2.1.5 Structure of port Pi (i = 1, 3 to 7, 9, A) direction register .................................... 2-4 2.1.6 Structure of port P8 direction register ...................................................................... 2-5 2.1.7 Structure of port PB direction register ...................................................................... 2-5 2.1.8 Structure of pull-up control register 1 ....................................................................... 2-6 2.1.9 Structure of pull-up control register 2 ....................................................................... 2-6 2.1.10 Structure of pull-up control register 3 ..................................................................... 2-7 2.2.1 Memory map of registers relevant to timers .......................................................... 2-11 2.2.2 Structure of Timer i (i=1, 3 to 6) ............................................................................. 2-12 2.2.3 Structure of Timer 2 .................................................................................................. 2-12 2.2.4 Structure of Timer 6 PWM register ......................................................................... 2-12 2.2.5 Structure of Timer 12 mode register ....................................................................... 2-13 2.2.6 Structure of Timer 34 mode register ....................................................................... 2-13 2.2.7 Structure of Timer 56 mode register ....................................................................... 2-14 2.2.8 Structure of Timer X (low-order, high-order) .......................................................... 2-15 2.2.9 Structure of Timer X mode register 1 ..................................................................... 2-16 2.2.10 Structure of Timer X mode register 2 ................................................................... 2-17 2.2.11 Structure of Interrupt request register 1 ............................................................... 2-18 2.2.12 Structure of Interrupt request register 2 ............................................................... 2-19 2.2.13 Structure of Interrupt control register 1 ................................................................ 2-20 2.2.14 Structure of Interrupt control register 2 ................................................................ 2-20 2.2.15 Timers connection and setting of division ratios ................................................. 2-22 2.2.16 Relevant registers setting ....................................................................................... 2-23 2.2.17 Control procedure..................................................................................................... 2-24 2.2.18 Peripheral circuit example ....................................................................................... 2-25 2.2.19 Timers connection and setting of division ratios ................................................. 2-25 2.2.20 Relevant registers setting ....................................................................................... 2-26 2.2.21 Control procedure..................................................................................................... 2-26 2.2.22 Judgment method of valid/invalid of input pulses ............................................... 2-27 2.2.23 Relevant registers setting ....................................................................................... 2-28 2.2.24 Control procedure..................................................................................................... 2-29 2.2.25 Timers connection and setting of division ratios ................................................. 2-30 2.2.26 Relevant registers setting ....................................................................................... 2-31 2.2.27 Control procedure..................................................................................................... 2-32 2.2.28 Timers connection and table example of timer X/RTP setting values ............. 2-34 2.2.29 RTP output example ................................................................................................ 2-34 2.2.30 Relevant registers setting ....................................................................................... 2-35 2.2.31 Control procedure..................................................................................................... 2-36
38B7 Group User's Manual
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List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.3.1 Memory map of registers relevant to Serial I/O .................................................... 2-37 2.3.2 Structure of Serial I/O1 automatic transfer data pointer ...................................... 2-38 2.3.3 Structure of Serial I/O1 control register 1 .............................................................. 2-39 2.3.4 Structure of Serial I/O1 control register 2 .............................................................. 2-40 2.3.5 Structure of Serial I/O1 register/Transfer counter ................................................. 2-41 2.3.6 Structure of Serial I/O1 control register 3 .............................................................. 2-42 2.3.7 Structure of Baud rate generator ............................................................................. 2-43 2.3.8 Structure of UART control register .......................................................................... 2-43 2.3.9 Structure of Serial I/O2 control register.................................................................. 2-44 2.3.10 Structure of Serial I/O2 status register ................................................................. 2-45 2.3.11 Structure of Serial I/O2 transmit/receive buffer register ..................................... 2-45 2.3.12 Structure of Serial I/O3 control register ................................................................ 2-46 2.3.13 Structure of Serial I/O3 register ............................................................................. 2-46 2.3.14 Structure of Interrupt source switch register ........................................................ 2-47 2.3.15 Structure of Interrupt request register 1 ............................................................... 2-47 2.3.16 Structure of Interrupt request register 2 ............................................................... 2-48 2.3.17 Structure of Interrupt control register 1 ................................................................ 2-49 2.3.18 Structure of Interrupt control register 2 ................................................................ 2-49 2.3.19 Serial I/O1 connection examples (1) ..................................................................... 2-50 2.3.20 Serial I/O1 connection examples (2) ..................................................................... 2-51 2.3.21 Serial I/O1's modes ................................................................................................. 2-52 2.3.22 Connection diagram ................................................................................................. 2-53 2.3.23 Timing chart .............................................................................................................. 2-53 2.3.24 Registers setting relevant to transmission side ................................................... 2-54 2.3.25 Setting of transmission data ................................................................................... 2-54 2.3.26 Control procedure..................................................................................................... 2-55 2.3.27 Connection diagram ................................................................................................. 2-56 2.3.28 Timing chart of serial data transmission/reception .............................................. 2-56 2.3.29 Relevant registers setting ....................................................................................... 2-57 2.3.30 Control procedure..................................................................................................... 2-58 2.3.31 Serial I/O2 connection examples (1) ..................................................................... 2-59 2.3.32 Serial I/O2 connection examples (2) ..................................................................... 2-60 2.3.33 Serial I/O2's modes ................................................................................................. 2-61 2.3.34 Serial I/O2 transfer data format ............................................................................. 2-61 2.3.35 Connection diagram ................................................................................................. 2-62 2.3.36 Timing chart .............................................................................................................. 2-62 2.3.37 Registers setting relevant to transmission side ................................................... 2-63 2.3.38 Registers setting relevant to reception side......................................................... 2-64 2.3.39 Control procedure of transmission side ................................................................ 2-65 2.3.40 Control procedure of reception side ...................................................................... 2-66 2.3.41 Connection diagram ................................................................................................. 2-67 2.3.42 Timing chart .............................................................................................................. 2-67 2.3.43 Relevant registers setting ....................................................................................... 2-68 2.3.44 Setting of transmission data ................................................................................... 2-68 2.3.45 Control procedure..................................................................................................... 2-69 2.3.46 Connection diagram ................................................................................................. 2-70 2.3.47 Timing chart .............................................................................................................. 2-71 2.3.48 Relevant registers setting in master unit .............................................................. 2-71 2.3.49 Relevant registers setting in slave unit ................................................................ 2-72 2.3.50 Control procedure of master unit ........................................................................... 2-73 2.3.51 Control procedure of slave unit ............................................................................. 2-74 2.3.52 Connection diagram ................................................................................................. 2-75
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List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.3.53 Timing chart .............................................................................................................. 2-75 2.3.54 Registers setting relevant to transmission side ................................................... 2-77 2.3.55 Registers setting relevant to reception side......................................................... 2-78 2.3.56 Control procedure of transmission side ................................................................ 2-79 2.3.57 Control procedure of reception side ...................................................................... 2-80 2.3.58 Serial I/O3 connection examples (1) ..................................................................... 2-81 2.3.59 Serial I/O3 connection examples (2) ..................................................................... 2-82 2.3.60 Serial I/O3's modes ................................................................................................. 2-83 2.3.61 Connection diagram ................................................................................................. 2-84 2.3.62 Timing chart .............................................................................................................. 2-84 2.3.63 Registers setting relevant to transmission side ................................................... 2-85 2.3.64 Setting of transmission data ................................................................................... 2-85 2.3.65 Control procedure..................................................................................................... 2-86 2.3.66 Sequence of setting serial I/O2 control register again ....................................... 2-90 2.4.1 Memory assignment of FLD controller relevant registers ..................................... 2-92 2.4.2 Structure of Port P0 digit output set switch register ............................................ 2-93 2.4.3 Structure of Port P2 digit output set switch register ............................................ 2-93 2.4.4 Structure of FLDC mode register............................................................................. 2-94 2.4.5 Structure of Tdisp time set register ......................................................................... 2-95 2.4.6 Structure of Toff1 time set register ......................................................................... 2-96 2.4.7 Structure of Toff2 time set register ......................................................................... 2-96 2.4.8 Structure of FLD data pointer/FLD data pointer reload register ......................... 2-97 2.4.9 Structure of port P4FLD/port switch register.......................................................... 2-97 2.4.10 Structure of port P5FLD/port switch register ....................................................... 2-98 2.4.11 Structure of port P6FLD/port switch register ....................................................... 2-98 2.4.12 Structure of FLD output control register ............................................................... 2-99 2.4.13 Structure of Interrupt request register 2 ............................................................. 2-100 2.4.14 Structure of Interrupt control register 2 .............................................................. 2-100 2.4.15 Connection diagram ............................................................................................... 2-101 2.4.16 Timing chart of key-scan using FLD automatic display mode and segments ................................................................................................................................. 2-101 2.4.17 Enlarged view of FLD0 (P20) to FLD7 (P27) Tscan ........................................... 2-101 2.4.18 Setting of relevant registers ................................................................................. 2-102 2.4.19 FLD digit allocation example ................................................................................ 2-105 2.4.20 Control procedure................................................................................................... 2-106 2.4.21 Connection diagram ............................................................................................... 2-108 2.4.22 Timing chart of key-scan using FLD automatic display mode and digits ...... 2-109 2.4.23 Setting of relevant registers ................................................................................. 2-110 2.4.24 FLD digit allocation example ................................................................................ 2-113 2.4.25 Control procedure................................................................................................... 2-114 2.4.26 Connection diagram ............................................................................................... 2-116 2.4.27 Timing chart of FLD display by software ........................................................... 2-116 2.4.28 Enlarged view of P20 to P27 key-scan ................................................................ 2-116 2.4.29 Setting of relevant registers ................................................................................. 2-117 2.4.30 FLD digit allocation example ................................................................................ 2-118 2.4.31 Control procedure................................................................................................... 2-119 2.4.32 Connection diagram ............................................................................................... 2-120 2.4.33 Timing chart of 38B7 Group and M35501FP ..................................................... 2-121 2.4.34 Timing chart (enlarged view) of digit and segment output .............................. 2-121 2.4.35 Setting of relevant registers ................................................................................. 2-122 2.4.36 FLD digit allocation example ................................................................................ 2-125 2.4.37 Control procedure................................................................................................... 2-125 2.4.38 Connection diagram ............................................................................................... 2-126
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List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.4.39 Timing chart (at correct state) of 38B7 Group and M35501FP ...................... 2-127 2.4.40 Timing chart (at incorrect state) of 38B7 Group and M35501FP ................... 2-127 2.4.41 Setting of relevant registers ................................................................................. 2-128 2.4.42 Control procedure................................................................................................... 2-130 2.5.1 Memory assignment of A-D converter relevant registers ................................... 2-133 2.5.2 Structure of AD/DA control register ....................................................................... 2-134 2.5.3 Structure of A-D conversion register (low-order) ................................................. 2-135 2.5.4 Structure of A-D conversion register (high-order) ............................................... 2-135 2.5.5 Structure of Interrupt source switch register ........................................................ 2-136 2.5.6 Structure of Interrupt request register 2 ............................................................... 2-136 2.5.7 Structure of Interrupt control register 2 ................................................................ 2-137 2.5.8 Connection diagram ................................................................................................. 2-138 2.5.9 Setting of relevant registers ................................................................................... 2-138 2.5.10 Control procedure................................................................................................... 2-139 2.6.1 Memory assignment of D-A converter relevant registers ................................... 2-141 2.6.2 Structure of D-A conversion register ..................................................................... 2-141 2.6.3 Structure of AD/DA control register ....................................................................... 2-142 2.6.4 Connection diagram ................................................................................................. 2-143 2.6.5 Setting of relevant registers ................................................................................... 2-143 2.6.6 Control procedure ..................................................................................................... 2-144 2.7.1 Memory assignment of PWM relevant registers .................................................. 2-145 2.7.2 Structure of PWM control register ......................................................................... 2-145 2.7.3 Structure of PWM register (high-order) ................................................................. 2-146 2.7.4 Structure of PWM register (low-order) .................................................................. 2-146 2.7.5 Connection diagram ................................................................................................. 2-147 2.7.6 Setting of relevant registers ................................................................................... 2-147 2.7.7 Control procedure ..................................................................................................... 2-148 2.7.8 PWM0 output ............................................................................................................. 2-148 2.8.1 Memory assignment of interrupt interval determination function relevant registers ................................................................................................................................... 2-149 2.8.2 Structure of Interrupt interval determination register .......................................... 2-149 2.8.3 Structure of Interrupt interval determination control register ............................. 2-150 2.8.4 Structure of Interrupt edge selection register ...................................................... 2-150 2.8.5 Structure of Interrupt request register 1 ............................................................... 2-151 2.8.6 Structure of Interrupt control register 1 ................................................................ 2-152 2.8.7 Connection diagram ................................................................................................. 2-153 2.8.8 Function block diagram ........................................................................................... 2-153 2.8.9 Timing chart of data determination ........................................................................ 2-153 2.8.10 Setting of relevant registers ................................................................................. 2-154 2.8.11 Control procedure................................................................................................... 2-155 2.8.12 Reception of remote-control data (timer 2 interrupt) ........................................ 2-156 2.9.1 Memory assignment of watchdog timer relevant register ................................... 2-157 2.9.2 Structure of Watchdog timer control register ....................................................... 2-157 2.9.3 Structure of CPU mode register ............................................................................ 2-158 2.9.4 Connection of watchdog timer and setting of division ratio ............................... 2-159 2.9.5 Setting of relevant registers ................................................................................... 2-159 2.9.6 Control procedure ..................................................................................................... 2-160 2.10.1 Memory assignment of buzzer output circuit relevant register ........................ 2-161 2.10.2 Structure of buzzer output control register......................................................... 2-161 2.10.3 Connection of buzzer output circuit and setting of division ratio.................... 2-162 2.10.4 Setting of relevant register ................................................................................... 2-162 2.10.5 Control procedure................................................................................................... 2-162
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List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.11.1 Example of power-on reset circuit ....................................................................... 2-163 2.11.2 RAM backup system example .............................................................................. 2-163 2.12.1 Structure of CPU mode register .......................................................................... 2-165 2.12.2 Connection diagram ............................................................................................... 2-166 2.12.3 Status transition diagram during power failure .................................................. 2-166 2.12.4 Setting of relevant registers ................................................................................. 2-167 2.12.5 Control procedure ................................................................................................... 2-168 2.12.6 Structure of clock counter ..................................................................................... 2-169 2.12.7 Initial setting of relevant registers ....................................................................... 2-170 2.12.8 Setting of relevant registers after detecting power failure ............................... 2-171 2.12.9 Control procedure ................................................................................................... 2-172 2.13.1 Memory map of flash memory version for 38B7 Group ................................... 2-174 2.13.2 Memory map of registers relevant to flash memory ......................................... 2-175 2.13.3 Structure of Flash memory control register ........................................................ 2-175 2.13.4 Structure of Flash command register .................................................................. 2-176 2.13.5 Structure of CPU mode register .......................................................................... 2-176 2.13.6 Reprogramming example of built-in flash memory by serial I/O mode .......... 2-179 2.13.7 Processing example of pins on board in serial I/O mode (1) ......................... 2-180 2.13.8 Processing example of pins on board in serial I/O mode (2) ......................... 2-180 2.13.9 Processing example of pins on board in serial I/O mode (3) ......................... 2-181 2.13.10 Example for reprogramming system of built-in flash memory by CPU reprogramming mode ....................................................................................................................... 2-182 2.13.11 CPU reprogramming control program example (1) ......................................... 2-183 2.13.12 CPU reprogramming control program example (2) ......................................... 2-184 2.13.13 CPU reprogramming control program example (3) ......................................... 2-185 2.13.14 CPU reprogramming control program example (4) ......................................... 2-186 2.13.15 VPP control circuit example (1) ........................................................................... 2-187 2.13.16 VPP control circuit example (2) ........................................................................... 2-187
CHAPTER 3 APPENDIX
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.1.1 3.1.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.3.9 Circuit for measuring output switching characteristics ............................................ 3-8 Timing diagram ............................................................................................................. 3-9 Power source current standard characteristics ...................................................... 3-10 Power source current standard characteristics (in wait mode) ........................... 3-10 High-breakdown P-channel open-drain output port characteristics (25 C) ....... 3-11 High-breakdown P-channel open-drain output port characteristics (90 C) ....... 3-11 CMOS output port P-channel side characteristics (25 C) .................................. 3-12 CMOS output port P-channel side characteristics (90 C) .................................. 3-12 CMOS output port N-channel side characteristics (25 C) .................................. 3-13 CMOS output port N-channel side characteristics (90 C) .................................. 3-13 A-D conversion standard characteristics ................................................................. 3-14 Setting procedure of relevant registers ................................................................... 3-15 Sequence of check of interrupt request bit ............................................................ 3-16 Structure of interrupt control register 2 .................................................................. 3-16 Sequence of setting serial I/O2 control register again ......................................... 3-20 PWM0 output ............................................................................................................... 3-22 Initialization of processor status register ................................................................ 3-24 Sequence of PLP instruction execution .................................................................. 3-24 Stack memory contents after PHP instruction execution ..................................... 3-24 Status flag at decimal calculations .......................................................................... 3-25
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List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. viii 3.4.1 Wiring for the RESET pin ......................................................................................... 3-28 3.4.2 Wiring for clock I/O pins ........................................................................................... 3-29 3.4.3 Wiring for CNVss pin ................................................................................................. 3-29 3.4.4 Wiring for the VPP pin of the flash memory version .............................................. 3-30 3.4.5 Bypass capacitor across the VSS line and the VCC line ........................................ 3-30 3.4.6 Analog signal line and a resistor and a capacitor ................................................ 3-31 3.4.7 Wiring for a large current signal line ...................................................................... 3-32 3.4.8 Wiring of signal lines where potential levels change frequently ......................... 3-32 3.4.9 VSS pattern on the underside of an oscillator ........................................................ 3-33 3.4.10 Setup for I/O ports ................................................................................................... 3-33 3.4.11 Watchdog timer by software ................................................................................... 3-34 3.5.1 Structure of Port Pi (i =0-7, 9, A)........................................................................... 3-35 3.5.2 Structure of Port P8................................................................................................... 3-35 3.5.3 Structure of Port PB .................................................................................................. 3-36 3.5.4 Structure of Port Pi direction register (i = 1, 3-7, 9, A) ...................................... 3-36 3.5.5 Structure of Port P8 direction register .................................................................... 3-37 3.5.6 Structure of Port PB direction register .................................................................... 3-37 3.5.7 Structure of Serial I/O1 automatic transfer data pointer ...................................... 3-38 3.5.8 Structure of Serial I/O1 control register 1 .............................................................. 3-38 3.5.9 Structure of Serial I/O1 control register 2 .............................................................. 3-39 3.5.10 Structure of Serial I/O1 register/Transfer counter ............................................... 3-40 3.5.11 Structure of Serial I/O1 control register 3 ............................................................ 3-41 3.5.12 Structure of Serial I/O2 control register ................................................................ 3-42 3.5.13 Structure of Serial I/O2 status register ................................................................. 3-43 3.5.14 Structure of Serial I/O2 transmit/receive buffer register ..................................... 3-43 3.5.15 Structure of Timer i ................................................................................................. 3-44 3.5.16 Structure of Timer 2 ................................................................................................ 3-44 3.5.17 Structure of PWM control register ......................................................................... 3-44 3.5.18 Structure of Timer 6 PWM register ....................................................................... 3-45 3.5.19 Structure of Timer 12 mode register ..................................................................... 3-45 3.5.20 Structure of Timer 34 mode register ..................................................................... 3-46 3.5.21 Structure of Timer 56 mode register ..................................................................... 3-46 3.5.22 Structure of D-A conversion register ..................................................................... 3-47 3.5.23 Structure of Timer X (low-order, high-order) ........................................................ 3-47 3.5.24 Structure of Timer X mode register 1 ................................................................... 3-48 3.5.25 Structure of Timer X mode register 2 ................................................................... 3-49 3.5.26 Structure of Interrupt interval determination register .......................................... 3-49 3.5.27 Structure of Interrupt interval determination control register ............................. 3-50 3.5.28 Structure of AD/DA control register ....................................................................... 3-51 3.5.29 Structure of A-D conversion register (low-order) ................................................. 3-51 3.5.30 Structure of A-D conversion register (high-order) ............................................... 3-52 3.5.31 Structure of PWM register (high-order)................................................................. 3-52 3.5.32 Structure of PWM register (low-order) .................................................................. 3-53 3.5.33 Structure of Baud rate generator ........................................................................... 3-53 3.5.34 Structure of UART control register ........................................................................ 3-54 3.5.35 Structure of Interrupt source switch register ........................................................ 3-55 3.5.36 Structure of Interrupt edge selection register ...................................................... 3-56 3.5.37 Structure of CPU mode register ............................................................................ 3-57 3.5.38 Structure of Interrupt request register 1 ............................................................... 3-58 3.5.39 Structure of Interrupt request register 2 ............................................................... 3-59 3.5.40 Structure of Interrupt control register 1 ................................................................ 3-60 3.5.41 Structure of Interrupt control register 2 ................................................................ 3-61 3.5.42 Structure of Serial I/O3 control register ................................................................ 3-62
38B7 Group User's Manual
List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.5.43 Structure of Serial I/O3 register ............................................................................. 3-62 3.5.44 Structure of Watchdog timer control register ....................................................... 3-63 3.5.45 Structure of Pull-up control register 3................................................................... 3-63 3.5.46 Structure of Pull-up control register 1................................................................... 3-64 3.5.47 Structure of Pull-up control register 2................................................................... 3-64 3.5.48 Structure of Port P0 digit output set switch register .......................................... 3-65 3.5.49 Structure of Port P2 digit output set switch register .......................................... 3-65 3.5.50 Structure of FLDC mode register .......................................................................... 3-66 3.5.51 Structure of Tdisp time set register ...................................................................... 3-67 3.5.52 Structure of Toff1 time set register ....................................................................... 3-68 3.5.53 Structure of Toff2 time set register ....................................................................... 3-68 3.5.54 Structure of FLD data pointer/FLD data pointer reload register ....................... 3-69 3.5.55 Structure of Port P4FLD/port switch register ....................................................... 3-69 3.5.56 Structure of Port P5FLD/port switch register ....................................................... 3-70 3.5.57 Structure of Port P6FLD/port switch register ....................................................... 3-70 3.5.58 Structure of FLD output control register ............................................................... 3-71 3.5.59 Structure of Buzzer output control register .......................................................... 3-72 3.5.60 Structure of Flash memory control register .......................................................... 3-73 3.5.61 Structure of Flash command register .................................................................... 3-74 3.9.1 Pin configuration of M35501FP ................................................................................ 3-88 3.9.2 Functional block diagram .......................................................................................... 3-89 3.9.3 Port block diagram ..................................................................................................... 3-90 3.9.4 Digit setting ................................................................................................................. 3-91 3.9.5 16-digit mode output waveform ................................................................................ 3-92 3.9.6 Optional digit mode output waveform...................................................................... 3-92 3.9.7 Cascade mode connection example: 17 digits or more selected ....................... 3-93 3.9.8 Cascade mode output waveform .............................................................................. 3-93 3.9.9 Connection example with 38B7 Group microcomputer (1 to 16 digits) ............. 3-94 3.9.10 Connection example with 38B7 Group microccomputer (17 to 32 digits) ....... 3-94 3.9.11 Digit output waveform when reset signal is input ............................................... 3-95 3.9.12 Power-on reset circuit .............................................................................................. 3-96 3.9.13 Timing diagram ......................................................................................................... 3-99
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List of tables
List of tables
CHAPTER 1 HARDWARE
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1 Pin description (1) ........................................................................................................... 1-5 2 Pin description (2) ........................................................................................................... 1-6 3 List of supported products ............................................................................................. 1-8 4 Push and pop instructions of accumulator or processor status register ............... 1-10 5 Set and clear instructions of each bit of processor status register ....................... 1-11 6 List of I/O port functions (1) ........................................................................................ 1-16 7 List of I/O port functions (2) ........................................................................................ 1-17 8 Interrupt vector addresses and priority ...................................................................... 1-22 9 FLD controller specifications ........................................................................................ 1-44 10 Pins in FLD automatic display mode ........................................................................ 1-50 11 Relationship between low-order 6-bit data and setting period of ADD bit ......... 1-64 12 Pin assignments of M38B79FF when operating in the parallel input/output mode ..................................................................................................................................... 1-78 13 Assignment states of control input and each state ................................................ 1-78 14 Pin description (flash memory parallel I/O mode) .................................................. 1-79 15 Software command (parallel input/output mode) ..................................................... 1-81 16 DC ELECTRICAL CHARACTERISTICS (Ta = 25 C, VCC = 5 V 10 %, unless otherwise noted) ......................................................................................................... 1-87 17 Read-only mode ........................................................................................................... 1-87 18 Read/Write mode ......................................................................................................... 1-87 19 Pin description (flash memory serial I/O mode) ..................................................... 1-89 20 Software command (serial I/O mode) ....................................................................... 1-90 21 AC Electrical characteristics ...................................................................................... 1-94
CHAPTER 2 APPLICATION
Table 2.1.1 Termination of unused pins ..................................................................................... 2-8 Table 2.3.1 Setting examples of baud rate generator values and transfer bit rate values ........................................................................................................................................................ 2-76 Table 2.3.2 SIO1CON3 (address 001C16) setting example selecting internal synchronous clock ........................................................................................................................................................ 2-88 Table 2.3.3 SIO1CON3 (address 001C16) setting example selecting external synchronous clock ........................................................................................................................................................ 2-88 Table 2.4.1 FLD automatic display RAM map ....................................................................... 2-104 Table 2.4.2 FLD automatic display RAM map example ....................................................... 2-105 Table 2.4.3 FLD automatic display RAM map ....................................................................... 2-112 Table 2.4.4 FLD automatic display RAM map example ....................................................... 2-113 Table 2.4.5 FLD automatic display RAM map example ....................................................... 2-118 Table 2.4.6 FLD automatic display RAM map ....................................................................... 2-124 Table 2.11.1 Pin state during "L" state of RESET pin ......................................................... 2-164 Table 2.13.1 Setting of EPROM programmer when parallel programming ........................ 2-177 Table 2.13.2 Connection example to programmer when serial programming ................... 2-177
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List of tables
CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2 Table 3.1.2 Recommended operating conditions (Vcc = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) ........................................ 3-2 Table 3.1.3 Recommended operating conditions (Vcc = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) ........................................ 3-3 Table 3.1.4 Electrical characteristics (Vcc = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) ........................................ 3-4 Table 3.1.5 Electrical characteristics (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = -20 to 85 C, unless otherwise noted) .................... 3-5 Table 3.1.6 A-D converter characteristics .................................................................................. 3-6 Table 3.1.7 D-A converter characteristics .................................................................................. 3-6 Table 3.1.8 Timing requirements (1) ........................................................................................... 3-7 Table 3.1.9 Switching characteristics .......................................................................................... 3-8 Table 3.3.1 SIO1CON3 (address 001C16) setting example selecting internal synchronous clock ........................................................................................................................................................ 3-19 Table 3.3.2 SIO1CON3 (address 001C16) setting example selecting external synchronous clock ........................................................................................................................................................ 3-19 Table 3.3.3 Pin state during "L" state of RESET pin ............................................................. 3-23 Table 3.9.1 Pin description ......................................................................................................... 3-89 Table 3.9.2 Absolute maximum ratings ..................................................................................... 3-97 Table 3.9.3 Recommended operating conditions (VCC = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) ..................................................................................................... 3-97 Table 3.9.4 Recommended operating conditions (VCC = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) ..................................................................................................... 3-97 Table 3.9.5 Electrical characteristics (VCC = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) ......................................................................................................................... 3-98 Table 3.9.6 Timing requirements (VCC = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) ........................................................................................................................ 3-98
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List of tables
MEMORANDUM
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CHAPTER 1 HARDWARE
DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING NOTES ON USAGE DATA REQUIRED FOR MASK ORDERS
HARDWARE
DESCRIPTION/FEATURES
DESCRIPTION
The 38B7 group is the 8-bit microcomputer based on the 740 family core technology. The 38B7 group has six 8-bit timers, one 16-bit timer, a fluorescent display automatic display circuit, 16-channel 10-bit A-D converter, a serial I/O with automatic transfer function, which are available for controlling musical instruments and household appliances. qSupply voltage ................................................. VCC = 5 V 10 % qProgram/Erase voltage ............................... VPP = 11.7 to 12.6 V qProgramming method ...................... Programming in unit of byte qErasing method Batch erasing ........................................ Parallel/Serial I/O mode Block erasing .................................... CPU reprogramming mode qProgram/Erase control by software command qNumber of times for programming/erasing ............................ 100 qOperating temperature range (at programming/erasing) ..................................................................... Normal temperature sNotes 1. The flash memory version cannot be used for application embedded in the MCU card. 2. Power source voltage Vcc of the flash memory version is 4.0 to 5.5 V.
FEATURES
Basic machine-language instructions ....................................... 71 The minimum instruction execution time .......................... 0.48 s (at 4.2 MHz oscillation frequency) Memory size ROM ........................................................ 60K bytes RAM ....................................................... 2048 bytes Programmable input/output ports ............................................. 75 High-breakdown-voltage output ports ...................................... 52 Software pull-up resistors . (Ports P64 to P67, P7, P80 to P83, P9, PA, PB) Interrupts .................................................. 22 sources, 16 vectors Timers ........................................................... 8-bit 6, 16-bit 1 Serial I/O1 (Clock-synchronized) ................................... 8-bit 1 (max. 256-byte automatic transfer function) Serial I/O2 (UART or Clock-synchronized) .................... 8-bit 1 Serial I/O3 (Clock-synchronized) ................................... 8-bit 1 PWM ............................................................................ 14-bit 1 8-bit 1 (also functions as timer 6) A-D converter .............................................. 10-bit 16 channels D-A converter ................................................................ 1 channel Fluorescent display function ......................... Total 56 control pins Interrupt interval determination function ..................................... 1 (Serviceable even in low-speed mode) Watchdog timer ............................................................ 16-bit 1 Buzzer output ............................................................................. 1 Two clock generating circuits Main clock (XIN-XOUT) .......................... Internal feedback resistor Sub-clock (XCIN-XCOUT) .......... Without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage In high-speed mode ................................................... 4.0 to 5.5 V (at 4.2 MHz oscillation frequency and high-speed selected) In middle-speed mode ........................................... 2.7 to 5.5 V (*) (at 4.2 MHz oscillation frequency and middle-speed selected) In low-speed mode ................................................ 2.7 to 5.5 V (*) (at 32 kHz oscillation frequency) (*: 4.0 to 5.5 V for Flash memory version) Power dissipation In high-speed mode .......................................................... 35 mW (at 4.2 MHz oscillation frequency) In low-speed mode ............................................................. 60 W (at 32 kHz oscillation frequency, at 3 V power source voltage) Operating temperature range ................................... -20 to 85 C
* * * * * * * * * * * * * * * * * * *
APPLICATION
Musical instruments, VCR, household appliances, etc.
*
*
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*P27/FLD7 *P26/FLD6 *P25/FLD5 *P24/FLD4 *P23/FLD3 *P22/FLD2 *P21/FLD1 *P20/FLD0 VEE PB6/SIN1 PB5/SOUT1 PB4/SCLK11 PB3/SSTB1 PB2/SBUSY1 PB1/SRDY1 PB0/SCLK12/DA AVSS VREF PA7/AN7 PA6/AN6
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Fig. 1 Pin configuration of M38B79MFH-XXXXFP
PIN CONFIGURATION (TOP VIEW)
Package type: 100P6S-A
M38B79MFH-XXXXFP
38B7 Group User's Manual
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 55 54 53 52 51
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 P97/BUZ02/AN15 P96/PWM0/AN14 P95/RTP0/AN13 P94/RTP1/AN12 P93/SRDY3/AN11 P92/SCLK3/AN10 P91/SOUT3/AN9 P90/SIN3/AN8 P83/CNTR0/CNTR2 P82/CNTR1 CNVSS RESET P81/XCOUT P80/XCIN VSS XIN XOUT VCC P77/INT4/BUZ01 P76/T3OUT P75/T1OUT P74/PWM1 P73/INT3/DIMOUT P72/INT2
*P00/FLD8 *P01/FLD9 *P02/FLD10 *P03/FLD11 *P04/FLD12 *P05/FLD13 *P06/FLD14 *P07/FLD15 *P10/FLD16 *P11/FLD17 *P12/FLD18 *P13/FLD19 *P14/FLD20 *P15/FLD21 *P16/FLD22 *P17/FLD23 *P30/FLD24 *P31/FLD25 *P32/FLD26 *P33/FLD27 *P34/FLD28 *P35/FLD29 *P36/FLD30 *P37/FLD31 *P40/FLD32 *P41/FLD33 *P42/FLD34 *P43/FLD35 *P44/FLD36 *P45/FLD37
*P46/FLD38 *P47/FLD39 *P50/FLD40 *P51/FLD41 *P52/FLD42 *P53/FLD43 *P54/FLD44 *P55/FLD45 *P56/FLD46 *P57/FLD47 *P60/FLD48 *P61/FLD49 *P62/FLD50 *P63/FLD51 P64/RxD/FLD52 P65/TxD/FLD53 P66/SCLK21/FLD54 P67/SRDY2/SCLK22/FLD55 P70/INT0 P71/INT1
*High-breakdown-voltage output port: Totaling 52
PIN CONFIGURATION
HARDWARE
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1-4
8 8 8 8 8 Port P4(8) Port P5(8) Port P3(8) Port P2(8) Port P1(8) Port P0(8) 8
FUNCTIONAL BLOCK DIAGRAM
HARDWARE
FUNCTIONAL BLOCK
Fig. 2 Functional block diagram
I/O ports
Build-in peripheral functions
A-D converter System clock generation Timers
(10-bit 12 channel)
Serial I/Os
Serial I/O1(Clock-synchronized) (256 byte automatic transfer)
Serial I/O2 (Clock-synchronized or UART)
Timer X(16-bit) Timer 1(8-bit) Timer 2(8-bit) Timer 3(8-bit) Timer 4(8-bit) Timer 5(8-bit) Timer 6(8-bit)
XIN-XOUT (main-clock) XCIN-XCOUT (sub-clock)
Serial I/O3(Clock-synchronized)
PWM1(8-bit) PWM0(14-bit)
Me mo r y CPU core
ROM
38B7 Group User's Manual
Buzzer output Watchdog timer RAM Interrupt interval determination function
FLD display function 56 control pins
(52 high-breakdown voltage ports)
Port P6(8) Port P7(8) 8 8
Port P8(4) 4
Port P9(8) 8
Port PA(8) 8
Port PB(7) 7
HARDWARE
PIN DESCRIPTION
Table 1 Pin description (1) Pin VCC, VSS CNVSS VEE VREF AVSS
______
Name Power source CNVSS Pull-down power source Reference voltage Analog power source Reset input Clock input
Function * Apply voltage of 4.0-5.5 V to VCC, and 0 V to VSS. * Connect to VSS. * VPP power input pin in flash memory mode. * Apply voltage supplied to pull-down resistors of ports P0, P1, P2 and P3. * Reference voltage input pin for A-D converter. * Analog power source input pin for A-D converter.
Function except a port function
RESET XIN
* Connect to VSS. * Reset input pin for active "L". * Input and output pins for the main clock generating circuit. * Feedback resistor is built in between XIN pin and XOUT pin. * Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. * When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. * The clock is used as the oscillating source of system clock. * 8-bit output port. * FLD automatic display * High-breakdown-voltage P-channel open-drain output structure. pins * A pull-down resistor is built in between port P0 and the VEE pin. * At reset, this port is set to VEE level. * 8-bit I/O port. * FLD automatic display * I/O direction register allows each pin to be individually programmed as either pins input or output. * At reset, this port is set to input mode. * Low-voltage input level. * High-breakdown-voltage P-channel open-drain output structure. * A pull-down resistor is built in between port P1 and the VEE pin. * At reset, this port is set to VEE level.
XOUT
Clock output
P00/FLD8- P07/FLD15
Output port P0
P10/FLD16- I/O port P1 P17/FLD23
P20/FLD0- P27/FLD7
Output port P2
P30/FLD24- P37/FLD31
I/O port P3
* 8-bit output port with the same function as port P0. * High-breakdown-voltage P-channel open-drain output structure. * A pull-down resistor is built in between port P2 and the VEE pin. * At reset, this port is set to VEE level. * 8-bit I/O port with the same function as port P1. * Low-voltage input level. * High-breakdown-voltage P-channel open-drain output structure. * A pull-down resistor is built in between port P3 and the VEE pin. * At reset, this port is set to VEE level. * 8-bit I/O port with the same function as port P1. * Low-voltage input level. * High-breakdown-voltage P-channel open-drain output structure. * A pull-down resistor is not built in between port P4 and the VEE pin. * 8-bit I/O port with the same function as port P1. * Low-voltage input level. * High-breakdown-voltage P-channel open-drain output structure. * A pull-down resistor is not built in between port P5 and the VEE pin. * 4-bit I/O port with the same function as port P1. * Low-voltage input level. * High-breakdown-voltage P-channel open-drain output structure. * A pull-down resistor is not built in between port P6 and the VEE pin.
* FLD automatic display pins
* FLD automatic display pins
P40/FLD32- I/O port P4 P47/FLD39
* FLD automatic display pins
P50/FLD40- I/O port P5 P57/FLD47
* FLD automatic display pins
P60/FLD48- I/O port P6 P63/FLD51
* FLD automatic display pins
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HARDWARE
PIN DESCRIPTION
Table 2 Pin description (2) Pin Name Function * 4-bit I/O port . * Low-voltage input level for input ports. * CMOS compatible input level for RxD, SCLK21, SCLK22. * CMOS 3-state output structure. * 8-bit I/O port. * CMOS compatible input level. * CMOS 3-state output structure. * Interrupt input pins Function except a port function * FLD automatic display pins * Serial I/O2 function pins
P64/RXD/FLD52, I/O port P6 P65/TXD/FLD53, P66/SCLK21/FLD54, P67/SRDY2/SCLK22/ FLD55, P70/INT0, I/O port P7 P71/INT1, P72/INT2, P73/INT3/DIMOUT, P74/PWM1 P75/T1OUT, P76/T3OUT, P77/INT4/BUZ01 P80/XCIN, P81/XCOUT I/O port P8
* Interrupt input pin * Dimmer signal output pin * PWM output pin * Timer output pins * Interrupt input pin * 4-bit I/O port with the same function as port P7. * CMOS compatible input level. * CMOS 3-state output structure. * Buzzer output pin * I/O pins for sub-clock generating
circuit (connect a ceramic resonator or a quarts-crystal oscillator)
P82/CNTR1, P83/CNTR0/CNTR2 P90/SIN3/AN8, I/O port P9 P91/SOUT3/AN9, P92/SCLK3/AN10, P93/SRDY3/AN11, P94/RTP1/AN12, P95/RTP0/AN13 P96/PWM0/AN14 P97/BUZ02/AN15 PA0/AN0-PA7/AN7 I/O port PA
* 8-bit I/O port with the same function as port P7. * CMOS compatible input level. * CMOS 3-state output structure.
* Timer input pin * Timer I/O pin * Serial I/O3 function pins * A-D converter input pins
* Real time port output pins * A-D converter input pins * 14-bit PWM output pin * A-D converter input pin * Buzzer output pin * A-D converter input pin * A-D converter input pin
PB0/SCLK12/DA
I/O port PB
* 8-bit I/O port with the same function as port P7. * CMOS compatible input level. * CMOS 3-state output structure. * 7-bit I/O port with the same function as port P7. * CMOS compatible input level. * CMOS 3-state output structure.
* Serial I/O1 function pin * D-A converter output pin * Serial I/O1 function pins
PB1/SRDY1, PB2/SBUSY1, PB3/SSTB1, PB4/SCLK11, PB5/SOUT1, PB6/SIN1
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HARDWARE
PART NUMBERING
Product M38B7 9 M F H - AXXX FP Package type FP : 100P6S-A package
ROM number Omitted in Flash memory version ROM/Flash memory size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used for users. Memory type M : Mask ROM version F : Flash memory version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes
Fig. 3 Part numbering
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HARDWARE
GROUP EXPANSION
GROUP EXPANSION
Mitsubishi plans to expand the 38B7 group as follows.
Memory Type
Support for Mask ROM and Flash memory versions.
Memory Size
Flash memory size ........................................................... 60K bytes Mask ROM size ................................................................ 60K bytes RAM size ......................................................................... 2048 bytes
Package
100P6S-A .................................. 0.65 mm-pitch plastic molded QFP
Mass product
ROM size (bytes) 60 K 56 K 52 K 48 K 44 K 40 K 36 K 32 K 28 K 24 K 20 K 16 K 12 K 8K 4K
256 512 768 1,024 1,536
M38B79FF M38B79MFH Mass product
2,048
RAM size (bytes)
Note : Products under development: the development schedule and specifications may be revised without notice. Fig. 4 Memory expansion plan Currently supported products are listed below. Table 3 List of supported products ROM size (bytes) Product ROM size for User ( ) M38B79MFH-XXXXFP 61440 (61310) M38B79FFFP As of Nov. 2001 RAM size (bytes) 2048 Package 100P6S-A Remarks Mask ROM version Flash memory version
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HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The 38B7 group uses the standard 740 Family instruction set. Refer to the table of 740 Series addressing modes and machine instructions or the 740 Series Software Manual for details on the instruction set. Machine-resident 740 Series instructions are as follows: The FST and SLW instructions cannot be used. The STP WIT, MUL, and DIV instructions can be used. ,
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is "0" , the high-order 8 bits becomes "0016". If the stack page selection bit is "1", the high-order 8 bits becomes "0116". The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address.
b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL
b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag
NVTBD I ZC
Fig. 5 740 Family CPU register structure
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HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request (Note) Execute JSR M (S) Push return address on stack (S) M (S) (S) (PCH) (S) - 1 (PCL) (S)- 1
M (S) (S) M (S) (S) M (S) (S)
(PCH) (S) - 1 (PCL) (S) - 1 (PS) (S) - 1 Push contents of processor status register on stack Push return address on stack
Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S)
Interrupt Service Routine
Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) (S) + 1 M (S)
I Flag is set from "0" to "1" Fetch the jump vector POP contents of processor status register from stack
POP return address from stack
Note: Condition for acceptance of an interrupt
Interrupt enable flag is "1" Interrupt disable flag is "0"
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP
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HARDWARE
FUNCTIONAL DESCRIPTION
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. *Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. *Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". *Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". *Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. *Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". *Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations. *Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. *Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag _ _ I flag SEI CLI D flag SED CLD B flag _ _ T flag SET CLT V flag _ CLV N flag _ _
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HARDWARE
FUNCTIONAL DESCRIPTION
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and the internal system clock selection bit etc. The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM: address 003B16)
Processor mode bits b1b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : Page 0 1 : Page 1 Not used (return "1" when read) (Do not write "0" to this bit.) Port XC switch bit 0 : I/O port function 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(XIN) (high-speed mode) 1 : f(XIN)/4 (middle-speed mode) Internal system clock selection bit 0 : XIN-XOUT selection (middle-/high-speed mode) 1 : XCIN-XCOUT selection (low-speed mode)
Fig. 7 Structure of CPU mode register
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HARDWARE
FUNCTIONAL DESCRIPTION
MEMORY Special Function Register (SFR) Area
The special function register (SFR) area contains control registers for I/O ports, timers and other functions.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
Special Page ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing, and the other areas are user areas for storing programs. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
RAM area
RAM size (byte) Address XXXX16
000016 RAM 004016 010016 SFR area 1 Zero page
192 256 384 512 640 768 896 1024 1536 2048 ROM area
ROM size (byte)
00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16
XXXX16 044016 0E0016 0EDF16 0EE016 0EFF16 0F0016 0FFF16 YYYY16
Reserved area Not used (Note)
RAM area for FLD automatic display
SFR area 2
RAM area for Serial I/O automatic transfer
Address YYYY16
Address ZZZZ16
4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440
F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016
F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016
ROM
Reserved ROM area
(common ROM area,128 bytes)
ZZZZ16
FF0016
FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area
Special page
Note: When 1024 bytes or more are used as RAM area, this area can be used.
Fig. 8 Memory map diagram
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FUNCTIONAL DESCRIPTION
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 0EEC16 0EED16 0EEE16 0EEF16 0EF016 0EF116 0EF216 0EF316 0EF416 0EF516
Port P0 (P0)
002016 002116
Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer 5 (T5) Timer 6 (T6) PWM control register (PWMCON) Timer 6 PWM register (T6PWM) Timer 12 mode register (T12M) Timer 34 mode register (T34M) Timer 56 mode register (T56M) D-A conversion register (DA) Timer X (low-order) (TXL) Timer X (high-order) (TXH) Timer X mode register 1 (TXM1) Timer X mode register 2 (TXM2) Interrupt interval determination register (IID)
Interrupt interval determination control register (IIDCON)
Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2)
002216 002316 002416 002516
Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) Port P9 (P9) Port P9 direction register (P9D) Port PA (PA) Port PA direction register (PAD) Port PB (PB) Port PB direction register (PBD)
Serial I/O1 automatic transfer data pointer (SIO1DP)
002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 0EF616 0EF716 0EF816 0EF916 0EFA16 0EFB16
AD/DA control register (ADCON) A-D conversion register (low-order) (ADL) A-D conversion register (high-order) (ADH) PWM register (high-order) (PWMH) PWM register (low-order) (PWML) Baud rate generator (BRG) UART control register (UARTCON) Interrupt source switch register (IFR) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Interrupt control register 2(ICON2) Toff1 time set register (TOFF1) Toff2 time set register (TOFF2) FLD data pointer (FLDDP) Port P4 FLD/Port switch register (P4FPR) Port P5 FLD/Port switch register (P5FPR) Port P6 FLD/Port switch register (P6FPR)
Serial I/O1 control register 1 (SIO1CON1) Serial I/O1 control register 2 (SIO1CON2) Serial I/O1 register/Transfer counter (SIO1) Serial I/O1 control register 3 (SIO1CON3) Serial I/O2 control register (SIO2CON) Serial I/O2 status register (SIO2STS)
Serial I/O2 transmit/receive buffer register (TB/RB)
Serial I/O3 control register (SIO3CON) Serial I/O3 register (SIO3) Watchdog timer control register (WDTCON) Pull-up control register 3 (PULL3) Pull-up control register 1 (PULL1) Pull-up control register 2 (PULL2) Port P0 digit output set switch register (P0DOR) Port P2 digit output set switch register (P2DOR) FLDC mode register (FLDM) Tdisp time set register (TDISP)
0EFC16 FLD output control register (FLDCON) 0EFD16 Buzzer output control register (BUZCON) 0EFE16 0EFF16 Flash memory control register (FCON) Flash command register (FCMD) Note: Flash memory version only. (Note) (Note)
Fig. 9 Memory map of special function register (SFR)
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FUNCTIONAL DESCRIPTION
I/O PORTS [Direction Registers] PiD
The 38B7 group has 75 programmable I/O pins arranged in ten individual I/O ports (P1, P3, P4, P5, P6, P7, P8, P9, PA and PB). The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that pin, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input (the bit corresponding to that pin must be set to "0") are floating and the value of that pin can be read. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.
[High-Breakdown-Voltage Output Ports]
The 38B7 group has seven ports with high-breakdown-voltage pins (ports P0 to P5 and P60-P63). The high-breakdown-voltage ports have P-channel open-drain output with Vcc - 45 V of breakdown voltage. Each pin in ports P0 to P3 has an internal pull-down resistor connected to VEE. At reset, the P-channel output transistor of each port latch is turned off, so that it goes to VEE level ("L") by the pull-down resistor. Writing "1" (weak drivability) to bit 7 of the FLDC mode register (address 0EF416) shows the rising transition of the output transistors for reducing transient noise. At reset, bit 7 of the FLDC mode register is set to "0" (strong drivability).
[Pull-up Control Register] PULL
Ports P64-P67, P7, P80-P83, P9, PA and PB have built-in programmable pull-up resistors. The pull-up resistors are valid only in the case that the each control bit is set to "1" and the corresponding port direction registers are set to input mode.
b7
b0
b7
b0
Pull-up control register 1 (PULL1 : address 0EF016) P64, P65 pull-up control bit P66, P67 pull-up control bit P70, P71 pull-up control bit P72, P73 pull-up control bit P74, P75 pull-up control bit P76, P77 pull-up control bit Not used (returns "0" when read) (Do not write "1".) 0: No pull-up 1: Pull-up
Pull-up control register 2 (PULL2 : address 0EF116) P80, P81 pull-up control bit P82, P83 pull-up control bit Not used (returns "0" when read) (Do not write "1".) P90, P91 pull-up control bit P92, P93 pull-up control bit P94, P95 pull-up control bit P96, P97 pull-up control bit Not used (returns "0" when read) (Do not write "1".) 0: No pull-up 1: Pull-up
b7
b0
Pull-up control register 3 (PULL3 : address 0EEF16) PA0, PA1 pull-up control bit PA2, PA3 pull-up control bit PA4, PA5 pull-up control bit PA6, PA7 pull-up control bit PB0, PB1 pull-up control bit PB2, PB3 pull-up control bit PB4, PB5 pull-up control bit PB6 pull-up control bit 0: No pull-up 1: Pull-up
Fig. 10 Structure of pull-up control registers (PULL1, PULL2 and PULL3)
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FUNCTIONAL DESCRIPTION
Table 6 List of I/O port functions (1) Pin P00/FLD8- P07/FLD15 Nama Port P0 Input/Output Output I/O Format High-breakdown voltage P-channel open-drain output with pull-down resistor Low-voltage input level High-breakdown voltage P-channel open-drain output with pull-down resistor High-breakdown voltage P-channel open-drain output with pull-down resistor Low-voltage input level High-breakdown voltage P-channel open-drain output with pull-down resistor Low-voltage input level High-breakdown voltage P-channel open-drain output Low-voltage input level High-breakdown voltage P-channel open-drain output Low-voltage input level High-breakdown voltage P-channel open-drain output Low-voltage input level (port input) CMOS compatible input level (RxD, SCLK21, SCLK22) CMOS 3-state output Non-Port Function FLD automatic display function Related SFRs FLDC mode register P0 digit output set switch register FLDC mode register Ref.No. (1)
P10/FLD16- P17/FLD23
Port P1
Input/output, individual bits
(2)
P20/FLD0- P27/FLD7
Port P2
Output
FLDC mode register P2 digit output set switch register FLDC mode register
(1)
P30/FLD24- P37/FLD31
Port P3
Input/output, individual bits
(2)
P40/FLD32- P47/FLD39
Port P4
Input/output, individual bits Input/output, individual bits Input/output, individual bits
FLDC mode register Port P4 FLD/Port switch register FLDC mode register Port P5 FLD/Port switch register FLDC mode register Port P6 FLD/Port switch register FLD automatic display function Serial I/O2 function I/O FLDC mode register Serial I/O2 control register UART control register
(2)
P50/FLD40- P57/FLD47
Port P5
(2)
P60/FLD48- P63/FLD51
Port P6
(2)
P64/RxD/ FLD52 P65/TxD/ FLD53, P66/SCLK21/ FLD54 P67/SRDY2/ SCLK22/ FLD55 P70/INT0, P71/INT1 P72/INT2
(3) (4)
(5)
Port P7
Input/output, individual bits
CMOS compatible input level CMOS 3-state output
External interrput input
Interrupt edge selection register Interrupt edge selection register Interrupt interval determination control register Interrupt edge selection register FLD output control register Timer 56 mode register Timer 12 mode register Timer 34 mode register Buzzer output control register Interrupt edge selection register CPU mode register Interrupt edge selection register
(6)
P73/INT3/ DIMOUT P74/PWM1 P75/T1OUT P76/T3OUT P77/INT4/ BUZ01
External interrput input Dimmer signal output PWM output Timer output Timer output Buzzer output External interrput input
(7)
(8)
(9)
P80/XCIN P81/XCOUT P82/CNTR1 P83/CNTR0/ CNTR2
Port P8
Input/output, individual bits
CMOS compatible input level CMOS 3-state output
Sub-clock generating circuit I/O External count input
(10) (11) (6) (12)
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Table 7 List of I/O port functions (2) Pin Nama Input/Output P90/SIN3/ Port P9 Input/output, AN8 individual bits P91/SOUT3/ AN9, P92/SCLK3/ AN10 P93/SRDY3/ AN11 P94/RTP1/ AN12, P95/RTP0/ AN13 P96/PWM0/ AN14 P97/BUZ02/ AN15 PA0/AN0- Port PA Input/output, PA7/AN7 individual bits PB0/SCLK12/ DA Port PB Input/output, individual bits I/O Format CMOS compatible input level CMOS 3-state output Non-Port Function Serial I/O3 function I/O A-D conversion input Related SFRs Serial I/O3 control register AD/DA control register Ref.No. (6) (13)
(14) Real time port output A-D conversion input Timer X mode register 2 AD/DA control register (15)
CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output
PWM output A-D conversion input Buzzer output A-D conversion input A-D conversion input
PWM control register AD/DA control register Buzzer output control register AD/DA control register AD/DA control register
(16) (16) (17)
Serial I/O1 function I/O D-A conversion output
Serial I/O1 function I/O PB1/SRDY1 PB2/SBUSY1 PB3/SSTB1 PB4/SCLK11 PB5/SOUT1 PB6/SIN1 Notes 1 : How to use double-function ports as function I/O ports, refer to the applicable sections. 2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
Serial I/O1 control registers 1, 2 AD/DA control register Serial I/O1 control registers 1, 2
(18)
(19) (18) (20) (21) (6)
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(1) Ports P0, P2 (2) Ports P1, P3, P4, P5, P60 to P63
FLD/Port switch register
P4, P5, P60 to P63
Dimmer signal (Note 1) Local data bus Data bus
Port latch Output
Local data bus Data bus
Dimmer signal (Note 1) Direction register Port latch
read
VEE
(Note 2) VEE
(3) Port P64
Dimmer signal (Note 1) Pull-up control
(4) Ports P65, P66
Pull-up control P-channel output disable signal (P65) Output OFF control signal Dimmer signal (Note 1) FLD/Port switch register
FLD/Port switch register
Local data bus Data bus
Direction register Serial I/O2 selection signal Direction register
Port latch
Local data bus Data bus
RxD input TxD or SCLK21 output Port latch
Serial clock input P66
(5) Port P67
Dimmer signal (Note 1) Pull-up control
(6) Ports P70 to P72, P82, P90, PB6
Pull-up control
FLD/Port switch register
Direction register
Local data bus Data bus
Direction register
Data bus
Port latch
Port latch
Serial ready output SRDY2 output enable bit Serial I/O2 enable bit Serial clock output Clock I/O pin selection bit Synchronous clock selection bit Serial clock input
INT0, INT1, INT2 interrupt input CNTR1 input Serial I/O input A-D conversion input
Analog input pin selection bit P90
High-breakdown-voltage P-channel transistor Notes 1: The dimmer signal sets the Toff timing. 2: A pull-down resistor is not built in to ports P4, P5 and P60 to P63.
Fig. 11 Port block diagram (1)
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(7) Port P73
Pull-up control Dimmer output control bit Direction register
(8) Ports P74 to P76
Timer 1 output selection bit Timer 3 output selection bit Timer 6 output selection bit Pull-up control
Direction register
Data bus
Port latch
Data bus
Port latch
Dimmer signal output INT3 interrupt input Timer 1 output Timer 3 output Timer 6 output
(9) Port P77
Pull-up control Buzzer control signal
(10) Port P80
Pull-up control Port Xc switch bit Direction register Direction register
Data bus
Port latch
Data bus
Port latch
Buzzer signal output INT4 interrupt input
Sub-clock generating circuit input
(11) Port P81
Pull-up control Port Xc switch bit
(12) Port P83
Pull-up control Timer X operating mode bits
Direction register Direction register
Data bus
Port latch
Data bus
Port latch
Oscillator
Port P80
Port Xc switch bit
Timer X output CNTR0, CNTR2 input
(13) Ports P91, P92
Pull-up control P-channel output disable signal (P91) Output OFF control signal Serial I/O3 selection signal Direction register
(14) Port P93
Pull-up control SRDY3 output enable bit
Direction register
Data bus
Port latch
Data bus
Port latch
SOUT or SCLK
Serial ready output
Serial clock input P92
A-D conversion input
A-D conversion input
Analog input pin selection bits Analog input pin selection bits
Fig. 12 Port block diagram (2)
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(15) Ports P94, P95
Pull-up control Real time port control bit Direction register PWM output selection bit Buzzer control signal Direction register
(16) Ports P96, P97
Pull-up control
Data bus
Port latch
Data bus
Port latch
RTP output A-D conversion input
PWM output Buzzer signal output A-D conversion input
Analog input pin selection bits
Analog input pin selection bits
(17) Port PA
Pull-up control
(18) Ports PB0, PB2
Pull-up control Serial I/O1 selection signal PB1/SRDY1*PB2/SBUSY1 pin control bit Direction register Direction register
Data bus
Port latch
Data bus
Port latch
SCLK12 output SBUSY1 output
A-D conversion input
Analog input pin selection bits
Serial clock input SBUSY1 input D-A converter output D-A output enable bit
PB0
(19) Port PB1
Pull-up control PB1/SRDY1*PB2/SBUSY1 pin control bit Direction register
(20) Port PB3
Pull-up control PB3/SSTB1 pin control bit
Direction register
Data bus
Port latch
Data bus
Port latch
Serial ready output Serial ready input
SSTB1 output
(21) Ports PB4, PB5
Pull-up control P-channel output disable signal (PB5) Output OFF control signal Serial I/O1 selection signal Direction register
Data bus
Port latch
SOUT or SCLK
Serial clock input PB4
Fig. 13 Port block diagram (3)
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INTERRUPTS
Interrupts occur by twenty two sources: five external, sixteen internal, and one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt has both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0." Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occur at the same time, the interrupt with highest priority is accepted first.
Interrupt Operation
Upon acceptance of an interrupt the following operations are automatically performed: 1. The contents of the program counter and processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter.
Interrupt Source Selection
Any of the following interrupt sources can be selected by the interrupt source switch register (address 003916). 1. INT1 or Serial I/O3 2. INT3 or Serial I/O2 transmit 3. INT4 or A-D conversion
sNote
When setting the followings, the interrupt request bit may be set to "1". *When switching external interrupt active edge Related register: Interrupt edge selection register (address 3A16) *When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt source switch register (address 3916) When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Set the interrupt edge select bit (active edge switch bit) or the interrupt (source) select/switch bit. Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. Set the corresponding interrupt enable bit to "1" (enabled).
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Table 8 Interrupt vector addresses and priority Interrupt Source Priority Reset (Note 2) INT0 INT1 1 2 3 Vector Addresses (Note 1) High FFFD16 FFFB16 FFF916 Low FFFC16 FFFA16 FFF816 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of data transfer At detection of either rising or falling edge of INT2 input At 8-bit counter overflow 5 FFF516 FFF416 At completion of data transfer At completion of the last data transfer 6 7 8 9 10 11 12 13 14 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 At timer X underflow At timer 1 underflow At timer 2 underflow At timer 3 underflow At timer 4 underflow At timer 5 underflow At timer 6 underflow At completion of serial I/O2 data receive At detection of either rising or falling edge of INT3 input Serial I/O2 transmit INT4 At completion of serial I/O2 data transmit At detection of either rising or falling edge of INT4 input A-D conversion FLD blanking At completion of A-D conversion At falling edge of the last timing immediately before blanking period starts Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when INT1 interrupt is selected Valid when serial I/O3 is selected External interrupt (active edge selectable) Valid when interrupt interval determination is operating Valid when serial I/O ordinary mode is selected Valid when serial I/O automatic transfer mode is selected Remarks
Serial I/O3 INT2 Remote control/ counter overflow Serial I/O1 Serial I/O automatic transfer Timer X Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 Serial I/O2 receive INT3
4
FFF716
FFF616
STP release timer underflow
External interrupt (active edge selectable) Valid when INT3 interrupt is selected External interrupt (active edge selectable) Valid when INT4 interrupt is selected Valid when A-D conversion is selected Valid when FLD blanking interrupt is selected Valid when FLD digit interrupt is selected Non-maskable software interrupt
15
FFE116
FFE016
16
FFDF16
FFDE16
FLD digit At rising edge of digit (each timing) BRK instruction 17 FFDD16 FFDC16 At BRK instruction execution Notes 1 : Vector addresses contain interrupt jump destination addresses. 2 : Reset function in the same way as an interrupt with the highest priority.
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Interrupt request bit Interrupt enable bit
Interrupt disable flag I
BRK instruction Reset
Interrupt request
Fig. 14 Interrupt control
b7
b0 Interrupt source switch register (IFR : address 003916) INT3/serial I/O2 transmit interrupt switch bit 0 : INT3 interrupt 1 : Serial I/O2 transmit interrupt INT4/AD conversion interrupt switch bit 0 : INT4 interrupt 1 : A-D conversion interrupt INT1/serial I/O3 interrupt switch bit 0 : INT1 interrupt 1 : Serial I/O3 interrupt Not used (return "0" when read) (Do not write "1" to these bits.)
b7
b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit INT4 interrupt edge selection bit Not used (return "0" when read) CNTR0 pin edge switch bit CNTR1 pin edge switch bit
0 : Falling edge active 1 : Rising edge active
0 : Rising edge count 1 : Falling edge count b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) Timer 4 interrupt request bit Timer 5 interrupt request bit Timer 6 interrupt request bit Serial I/O2 receive interrupt request bit INT3/serial I/O2 transmit interrupt request bit INT4 interrupt request bit AD conversion interrupt request bit FLD blanking interrupt request bit FLD digit interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 2 (ICON2 : address 003F16) Timer 4 interrupt enable bit Timer 5 interrupt enable bit Timer 6 interrupt enable bit Serial I/O2 receive interrupt enable bit INT3/serial I/O2 transmit interrupt enable bit INT4 interrupt enable bit AD conversion interrupt enable bit FLD blanking interrupt enable bit FLD digit interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit.) 0 : Interrupt disabled 1 : Interrupt enabled
b7
b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O3 interrupt request bit INT2 interrupt request bit Remote controller/counter overflow interrupt request bit Serial I/O1 interrupt request bit
Serial I/O automatic transfer interrupt request bit
Timer X interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O3 interrupt enable bit INT2 interrupt enable bit Remote controller/counter overflow interrupt enable bit Serial I/O1 interrupt enable bit
Serial I/O automatic transfer interrupt enable bit
Timer X interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit
Fig. 15 Structure of interrupt related registers
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TIMERS 8-Bit Timer
The 38B7 group has six built-in 8-bit timers : Timer 1, Timer 2, Timer 3, Timer 4, Timer 5, and Timer 6. Each timer has the 8-bit timer latch. All timers are down-counters. When the timer reaches "0016", an underflow occurs with the next count pulse. Then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1". The count can be stopped by setting the stop bit of each timer to "1". The internal system clock can be set to either the high-speed mode or low-speed mode with the CPU mode register. At the same time, the timer internal count source is switched to either f(XIN) or f(XCIN). qTimer 1, Timer 2 The count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. A rectangular waveform of timer 1 underflow signal divided by 2 can be output from the P75/T1OUT pin. The active edge of the external clock CNTR0 can be switched with the bit 6 of the interrupt edge selection register. At reset or when executing the STP instruction, all bits of the timer 12 mode register are cleared to "0", timer 1 is set to "FF16", and timer 2 is set to "0116". qTimer 3, Timer 4 The count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. A rectangular waveform of timer 3 underflow signal divided by 2 can be output from the P76/T3OUT pin. The active edge of the external clock CNTR1 can be switched with the bit 7 of the interrupt edge selection register. qTimer 5, Timer 6 The count sources of timer 5 and timer 6 can be selected by setting the timer 56 mode register. A rectangular waveform of timer 6 underflow signal divided by 2 can be output from the P74/PWM1 pin.
b7 b0 b7 b0
Timer 12 mode register (T12M: address 002816) Timer 1 count stop bit 0 : Count operation 1 : Count stop Timer 2 count stop bit 0 : Count operation 1 : Count stop Timer 1 count source selection bits 00 : f(XIN)/8 or f(XCIN)/16 01 : f(XCIN) 10 : f(XIN)/16 or f(XCIN)/32 11 : f(XIN)/64 or f(XCIN)/128 Timer 2 count source selection bits 00 : Underflow of Timer 1 01 : f(XCIN) 10 : External count input CNTR0 11 : Not available Timer 1 output selection bit (P75) 0 : I/O port 1 : Timer 1 output Not used (returns "0" when read) (Do not write "1" to this bit.)
b7 b0
Timer 34 mode register (T34M: address 002916) Timer 3 count stop bit 0 : Count operation 1 : Count stop Timer 4 count stop bit 0 : Count operation 1 : Count stop Timer 3 count source selection bits 00 : f(XIN)/8 or f(XCIN)/16 01 : Underflow of Timer 2 10 : f(XIN)/16 or f(XCIN)/32 11 : f(XIN)/64 or f(XCIN)/128 Timer 4 count source selection bits 00 : f(XIN)/8 or f(XCIN)/16 01 : Underflow of Timer 3 10 : External count input CNTR1 11 : Not available Timer 3 output selection bit (P76) 0 : I/O port 1 : Timer 3 output Not used (returns "0" when read) (Do not write "1" to this bit.)
qTimer 6 PWM1 Mode Timer 6 can output a PWM rectangular waveform with "H" duty cycle n/(n+m) from the P74/PWM1 pin by setting the timer 56 mode register (refer to Figure 18). The n is the value set in timer 6 latch (address 002516) and m is the value in the timer 6 PWM register (address 002716). If n is "0," the PWM output is "L", if m is "0", the PWM output is "H" (n = 0 is prior than m = 0). In the PWM mode, interrupts occur at the rising edge of the PWM output.
Timer 56 mode register (T56M: address 002A16) Timer 5 count stop bit 0 : Count operation 1 : Count stop Timer 6 count stop bit 0 : Count operation 1 : Count stop Timer 5 count source selection bit 0 : f(XIN)/8 or f(XCIN)/16 1 : Underflow of Timer 4 Timer 6 operation mode selection bit 0 : Timer mode 1 : PWM mode Timer 6 count source selection bits 00 : f(XIN)/8 or f(XCIN)/16 01 : Underflow of Timer 5 10 : Underflow of Timer 4 11 : Not available Timer 6 (PWM) output selection bit (P74) 0 : I/O port 1 : Timer 6 output Not used (returns "0" when read) (Do not write "1" to this bit.)
Fig. 16 Structure of timer related registers
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Data bus
XCIN 1/2 "1" XIN "0"
Internal system clock selection bit Timer 1 latch (8) RESET STP instruction Timer 1 interrupt request Timer 1 count source Timer 1 (8)
"01" selection bits "00" "10" "11"
FF16
1/8 1/16 1/64
Timer 1 count stop bit
P75/T1OUT
P75 latch
1/2
Timer 1 output selection bit Timer 2 latch (8) Timer 2 count source selection bits Timer 2 (8) P75 direction register
"00" "01" "10" CNTR0 P83/CNTR0/CNTR2
Rising/Falling active edge switch
0116 Timer 2 interrupt request
Timer 2 count stop bit
CNTR2
Timer 3 latch (8) Timer 3 count source selection bits Timer 3 (8) Timer 3 count stop bit Timer 3 interrupt request
"01" "00" P76/T3OUT
P76 latch
"10" "11"
1/2
Timer 3 output selection bit Timer 4 latch (8)
"01"
P76 direction register
Timer 4 count source selection bits Timer 4 (8) Timer 4 count stop bit Timer 4 interrupt request
"00" "10"
P82/CNTR1
Rising/Falling active edge switch
Timer 5 latch (8)
"1" "0"
Timer 5 count source selection bit Timer 5 (8) Timer 5 count stop bit Timer 5 interrupt request
Timer 6 latch (8)
"01" "00" "10"
Timer 6 count source selection bits Timer 6 (8) Timer 6 count stop bit Timer 6 interrupt request
Timer 6 PWM register (8)
P74/PWM1
P74 latch
"1" "0"
Timer 6 output selection bit
PWM
1/2
Timer 6 operation mode selection bit
P74 direction register
Fig. 17 Block diagram of timer
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ts Timer 6 count source
Timer 6 PWM mode n ts m ts (n+m) ts
Timer 6 interrupt request
Timer 6 interrupt request
Note: PWM waveform (duty : n/(n + m) and period: (n + m) ts) is output. n : setting value of Timer 6 m: setting value of Timer 6 PWM register ts: period of Timer 6 count source
Fig. 18 Timing chart of timer 6 PWM1 mode
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16-Bit Timer
Timer X is a 16-bit timer that can be selected in one of four modes by the Timer X mode registers 1, 2 and can be controlled for the timer X write and the real time port by setting the timer X mode registers. Read and write operation on 16-bit timer must be performed for both high- and low-order bytes. When reading a 16-bit timer, read from the high-order byte first. When writing to 16-bit timer, write to the loworder byte first. The 16-bit timer cannot perform the correct operation when reading during write operation, or when writing during read operation. qTimer X Timer X is a down-counter. When the timer reaches "000016", an underflow occurs with the next count pulse. Then the contents of the timer latch is reloaded into the timer and the timer continues downcounting. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1". (1) Timer mode A count source can be selected by setting the Timer X count source selection bits (bits 1 and 2) of the Timer X mode register 1. (2) Pulse output mode Each time the timer underflows, a signal output from the CNTR2 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR2 pin to output. (3) Event counter mode The timer counts signals input through the CNTR2 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR2 pin to input. (4) Pulse width measurement mode A count source can be selected by setting the Timer X count source selection bits (bits 1 and 2) of the Timer X mode register 1. When CNTR2 active edge switch bit is "0", the timer counts while the input signal of the CNTR2 pin is at "H". When it is "1", the timer counts while the input signal of the CNTR2 pin is at "L". When using a timer in this mode, set the port shared with the CNTR2 pin to input.
s Note
*Timer X Write Control If the timer X write control bit is "0", when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is "1", when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. When the value is written in latch only, unexpected value may be set in the high-order counter if the writing in high-order latch and the underflow of timer X are performed at the same timing. *Real Time Port Control While the real time port function is valid, data for the real time port are output from ports P94 and P95 each time the timer X underflows. (However, if the real time port control bit is changed from "0" to "1", data are output independent of the timer X.) When the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode.
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FUNCTIONAL DESCRIPTION
Real time port control bit "1" P94
Data bus QD P94 data for real time port Real time port control bit (P94) "0" "1 " Timer X mode register write signal
"0 " Latch P94 direction register P94 latch Real time port control bit "1" QD P95 "0 " Latch P95 direction register P95 latch
P95 data for real time port Real time port control bit (P95) "0" "1 "
XCIN
1/2 "1"
Timer X mode register write signal
XIN
Internal system clock selection bit 1/2 Count source selection bit 1/8 "0 " 1/64 Timer X stop control bit Timer X operating
Divider
Timer X write control bit
CNTR2 active edge switch bit P83/CNTR0/CNTR2
mode bits
"0"
"00","01","11" "10"
Timer X latch (low-order) (8) Timer X latch (high-order) (8) Timer X (low-order) (8) Timer X (high-order) (8)
Timer X interrupt request
"1" Pulse width measurement mode CNTR2 active edge switch bit "0" Q P83 direction register "1" P83 latch Q
Pulse output mode S T
Pulse output mode CNTR0
Fig. 19 Block diagram of timer X
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 1 (TXM1 : address 002E16) Timer X write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer X count source selection bits b2 b1 0 0 : f(XIN)/2 or f(XCIN)/4 0 1 : f(XIN)/8 or f(XCIN)/16 1 0 : f(XIN)/64 or f(XCIN)/128 1 1 : Not available Not used (returns "0" when read) Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR2 active edge switch bit 0 : * Event counter mode ; counts rising edges * Pulse output mode ; output starts with "H" level * Pulse width measurement mode ; measures "H" periods 1 : * Event counter mode ; counts falling edges * Pulse output mode ; output starts with "L" level * Pulse width measurement mode ; measures "L" periods Timer X stop control bit 0 : Count operating 1 : Count stop
Timer X mode register 2 (TXM2 : address 002F16) Real time port control bit (P94) 0 : Real time port function is invalid 1 : Real time port function is valid Real time port control bit (P95) 0 : Real time port function is invalid 1 : Real time port function is valid P94 data for real time port P95 data for real time port Not used (returns "0" when read)
Fig. 20 Structure of timer X related registers
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FUNCTIONAL DESCRIPTION
SERIAL I/O Serial I/O1
Serial I/O1 is used as the clock synchronous serial I/O and has an ordinary mode and an automatic transfer mode. In the automatic transfer mode, serial transfer is performed through the serial I/O automatic transfer RAM which has up to 256 bytes (addresses 0F0016 to 0FFF16). The PB1/SRDY1, PB2/SBUSY1, and PB3/SSTB1 pins each have a handshake I/O signal function and can select either "H" active or "L" active for active logic.
Main address bus
Local address bus
Serial I/O automatic transfer RAM (0F0016 to 0FFF16)
Main Local data bus data bus
Address decoder
Serial I/O1 automatic transfer data pointer Serial I/O1 automatic transfer controller
XCIN
1/2
Internal system clock selection bit "1 " "0 "
Serial I/O1 control register 3
1/4 1/8 1/16 1/32 1/64 1/128 1/256
XIN
"0 "
(PB3/SSTB1 pin control bit)
PB3/SSTB1
"1"
PB1/SRDY1*PB2/SBUSY1 PB2 latch pin control bit "0"
PB2/SBUSY1
"1" PB1/SRDY1*PB2/SBUSY1 PB1 latch pin control bit "0 "
Serial I/O1 synchronous clock selection bit Synchronous circuit
"0" "1"
Serial I/O1 clock pin selection bit
PB1/SRDY1
"1"
SCLK1
"0 "
"1"
Divider
PB3 latch
Internal synchronous clock selection bits
Serial transfer status flag PB4 latch
"0 "
Serial I/O1 interrupt request
PB4/SCLK11
"1" "1 "
"0 "
Serial I/O1 counter
"1"
Serial I/O1 clock pin selection bits
PB0/SCLK12
"0 "
PB0 latch
"0"
PB5/SOUT1
PB5 latch
"1" Serial transfer selection bits
PB6/SIN1
Serial I/O1 register (8)
Fig. 21 Block diagram of serial I/O1
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FUNCTIONAL DESCRIPTION
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 1 (SIO1CON1 (SC11):address 001916) Serial transfer selection bits
b1 b0
0 0 : Serial I/O disabled (pins PB0 to PB6 are I/O ports) 0 1 : 8-bit serial I/O 1 0 : Not available 1 1 : Automatic transfer serial I/O (8-bits) Serial I/O1 synchronous clock selection bits (PB3/SSTB1 pin control bit)
b3 b2
0 0 : Internal synchronous clock (PB3 pin is an I/O port.) 0 1 : External synchronous clock (PB3 pin is an I/O port.) 1 0 : Internal synchronous clock (PB3 pin is an SSTB1 output.) 1 1 : Internal synchronous clock (PB3 pin is an SSTB1 output.) Serial I/O initialization bit 0: Serial I/O initialization 1: Serial I/O enabled Transfer mode selection bit 0: Full duplex (transmit and receive) mode (PB6 pin is an SIN1 input.) 1: Transmit-only mode (PB6 pin is an I/O port.) Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O1 clock pin selection bit 0:SCLK11 (PB0/SCLK12 pin is an I/O port.) 1:SCLK12 (PB4/SCLK11 pin is an I/O port.)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 2 (SIO1CON2 (SC12): address 001A16) PB1/SRDY1 * PB2/SBUSY1 pin control bits
b3b2b1b0
0 0 0 0: Pins PB1 and PB2 are I/O ports 0 0 0 1: Not used 0 0 1 0: PB1 pin is an SRDY1 output, PB2 pin is an I/O port. 0 0 1 1: PB1 pin is an SRDY1 output, PB2 pin is an I/O port. 0 1 0 0: PB1 pin is an I/O port, PB2 pin is an SBUSY1 input. 0 1 0 1: PB1 pin is an I/O port, PB2 pin is an SBUSY1 input. 0 1 1 0: PB1 pin is an I/O port, PB2 pin is an SBUSY1 output. 0 1 1 1: PB1 pin is an I/O port, PB2 pin is an SBUSY1 output. 1 0 0 0: PB1 pin is an SRDY1 input, PB2 pin is an SBUSY1 output. 1 0 0 1: PB1 pin is an SRDY1 input, PB2 pin is an SBUSY1 output. 1 0 1 0: PB1 pin is an SRDY1 input, PB2 pin is an SBUSY1 output. 1 0 1 1: PB1 pin is an SRDY1 input, PB2 pin is an SBUSY1 output. 1 1 0 0: PB1 pin is an SRDY1 output, PB2 pin is an SBUSY1 input. 1 1 0 1: PB1 pin is an SRDY1 output, PB2 pin is an SBUSY1 input. 1 1 1 0: PB1 pin is an SRDY1 output, PB2 pin is an SBUSY1 input. 1 1 1 1: PB1 pin is an SRDY1 output, PB2 pin is an SBUSY1 input. SBUSY1 output * SSTB1 output function selection bit (Valid in automatic transfer mode) 0: Functions as each 1-byte signal 1: Functions as signal for all transfer data Serial transfer status flag 0: Serial transfer completion 1: Serial transferring SOUT1 pin control bit (at no-transfer serial data) 0: Output active 1: Output high-impedance PB5/SOUT1 P-channel output disable bit 0: CMOS 3-state (P-channel output is valid.) 1: N-channel open-drain (P-channel output is invalid.)
Fig. 22 Structure of serial I/O1 control registers 1, 2
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FUNCTIONAL DESCRIPTION
(1) Serial I/O1 operation
Either the internal synchronous clock or external synchronous clock can be selected by the serial I/O1 synchronous clock selection bits (b2 and b3 of address 001916) of serial I/O1 control register 1 as synchronous clock for serial transfer. The internal synchronous clock has a built-in dedicated divider where 7 different clocks are selected by the internal synchronous clock selection bits (b5, b6 and b7 of address 001C16) of serial I/O1 control register 3. The PB1/SRDY1, PB2/SBUSY1, and PB3/SSTB1 pins each select either I/O port or handshake I/O signal by the serial I/O1 synchronous clock selection bits (b2 and b3 of address 001916) of serial I/O1 control register 1 as well as the PB1/SRDY1 * PB2/ SBUSY1 pin control bits (b0 to b3 of address 001A16) of serial I/O1 control register 2. For the SOUT1 being used as an output pin, either CMOS output or N-channel open-drain output is selected by the PB5/SOUT1 Pchannel output disable bit (b7 of address 001A16) of serial I/O1 control register 2. Either output active or high-impedance can be selected as a SOUT1 pin state at serial non-transfer by the SOUT1 pin control bit (b6 of address 001A16) of serial I/O1 control register 2. However, when the external synchronous clock is selected, perform the following setup to put the SOUT1 pin into a high-impedance state: When the SCLK1 input is "H" after completion of transfer, set the SOUT1 pin control bit to "1". When the SCLK1 input goes to "L" after the start of the next serial transfer, the SOUT1 pin control bit is automatically reset to "0" and put into an output active state. Regardless of whether the internal synchronous clock or external synchronous clock is selected, the full duplex mode and the transmit-only mode are available for serial transfer, one of which is selected by the transfer mode selection bit (b5 of address 001916) of serial I/O1 control register 1. Either LSB first or MSB first is selected for the I/O sequence of the serial transfer bit strings by the transfer direction selection bit (b6 of address 001916) of serial I/O1 control register 1. When using serial I/O1, first select either 8-bit serial I/O or automatic transfer serial I/O by the serial transfer selection bits (b0 and b1 of address 001916) of serial I/O1 control register 1, after completion of the above bit setup. Next, set the serial I/O initialization bit (b4 of address 001916) of serial I/O1 control register 1 to "1" (Serial I/O enable) . When stopping serial transfer while data is being transferred, regardless of whether the internal or external synchronous clock is selected, reset the serial I/O initialization bit (b4) to "0".
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 3 (SIO1CON3 (SC13): address 001C16) Automatic transfer interval set bits
b4b3b2b1b0
0 0 0 0 0: 2 cycles of transfer clocks 0 0 0 0 1: 3 cycles of transfer clocks : 1 1 1 1 0: 32 cycles of transfer clocks 1 1 1 1 1: 33 cycles of transfer clocks Data is written to a latch and read from a decrement counter. Internal synchronous clock selection bits
b7b6b5
0 0 0: f(XIN)/4 or f(XCIN)/8 0 0 1: f(XIN)/8 or f(XCIN)/16 0 1 0: f(XIN)/16 or f(XCIN)/32 0 1 1: f(XIN)/32 or f(XCIN)/64 1 0 0: f(XIN)/64 or f(XCIN)/128 1 0 1: f(XIN)/128 or f(XCIN)/256 1 1 0: f(XIN)/256 or f(XCIN)/512
Fig. 23 Structure of serial I/O1 control register 3
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FUNCTIONAL DESCRIPTION
(2) 8-bit serial I/O mode
Address 001B16 is assigned to the serial I/O1 register. When the internal synchronous clock is selected, a serial transfer of the 8-bit serial I/O is started by a write signal to the serial I/O1 register (address 001B16). The serial transfer status flag (b5 of address 001A16) of serial I/O1 control register 2 indicates the shift register status of serial I/O1, and is set to "1" by writing into the serial I/O1 register, which becomes a transfer start trigger and reset to "0" after completion of 8-bit transfer. At the same time, a serial I/O1 interrupt request occurs. When the external synchronous clock is selected, the contents of the serial I/O1 register are continuously shifted while transfer clocks are input to SCLK1. Therefore, the clock needs to be controlled externally. I/O1 control register 2 as the signal for all transfer data, provided that the automatic transfer interval setting is valid, a transfer interval is placed before the start of transmission/reception of the first data and after the end of transmission/reception of the last data. For SSTB1 output, regardless of the contents of the SBUSY1 output * SSTB1 output function selection bit (b4), the transfer interval for each 1-byte data is longer than the set value by 2 cycles. Furthermore, when using a combination of SBUSY1 output and SSTB1 output as a signal for all transfer data, the transfer interval after the end of transmission/reception of the last data is longer than the set value by 2 cycles. When the external synchronous clock is selected, automatic transfer interval setting is disabled. After completion of the above bit setup, if the internal synchronous clock is selected, automatic serial transfer is started by writing the value of "number of transfer bytes - 1" into the transfer counter (address 001B16). When the external synchronous clock is selected, write the value of "number of transfer bytes - 1" into the transfer counter and keep an internal system clock interval of 5 cycles or more. After that, input transfer clock to SCLK1. As a transfer interval for each 1-byte data transfer, keep an internal system clock interval of 5 cycles or more from the clock rise time of the last bit. Regardless of whether the internal or external synchronous clock is selected, the automatic transfer data pointer and the transfer counter are decremented after each 1-byte data is received and then written into the automatic transfer RAM. The serial transfer status flag (b5 of address 001A16) is set to "1" by writing data into the transfer counter. Writing data becomes a transfer start trigger, and the serial transfer status flag is reset to "0" after the last data is written into the automatic transfer RAM. At the same time, a serial I/O1 interrupt request occurs. The values written in the automatic transfer data pointer set bits (b0 to b7 of address 001816) and the automatic transfer interval set bits (b0 to b4 of address 001C16) are held in the latch. When data is written into the transfer counter, the values latched in the automatic transfer data pointer set bits (b0 to b7) and the automatic transfer interval set bits (b0 to b4) are transferred to the decrement counter.
(3) Automatic transfer serial I/O mode
The serial I/O1 automatic transfer controller controls the write and read operations of the serial I/O1 register, so that the function of address 001B16 is used as a transfer counter (1-byte unit). When performing serial transfer through the serial I/O automatic transfer RAM (addresses 0F0016 to 0FFF16), it is necessary to set the serial I/O1 automatic transfer data pointer (address 001816) beforehand. Input the low-order 8 bits of the first data store address to be serially transferred to the automatic transfer data pointer set bits. When the internal synchronous clock is selected, the transfer interval for each 1-byte data can be set by the automatic transfer interval set bits (b0 to b4 of address 001C16) of serial I/O1 control register 3 in the following cases: 1. When using no handshake signal 2. When using the SRDY1 output, SBUSY1 output, and SSTB1 output of the handshake signal independently 3. When using a combination of SRDY1 output and SSTB1 output or a combination of SBUSY1 output and SSTB1 output of the handshake signal. It is possible to select one of 32 different values, namely 2 to 33 cycles of the transfer clock, as a setting value. When using the SBUSY1 output and selecting the SBUSY1 output * SSTB1 output function selection bit (b4 of address 001A16) of serial
b7
b0 Serial I/O1 automatic transfer data pointer (SIO1DP: address 001816) Automatic transfer data pointer set bits Specify the low-order 8 bits of the first data store address on the serial I/O automatic transfer RAM. Data is written into the latch and read from the decrement counter.
Fig. 24 Structure of serial I/O1 automatic transfer data pointer
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FUNCTIONAL DESCRIPTION
Automatic transfer RAM FFF16
Automatic transfer data pointer
5216
F5216 F5116 F5016 F4F16 F4E16
Transfer counter
0416
F0016
SIN1
Serial I/O1 register
SOUT1
Fig. 25 Automatic transfer serial I/O operation
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FUNCTIONAL DESCRIPTION
(4) Handshake signal
1. SSTB1 output signal The SSTB1 output is a signal to inform an end of transmission/reception to the serial transfer destination . The SSTB1 output signal can be used only when the internal synchronous clock is selected. In the initial status, namely, in the status in which the serial I/O initialization bit (b4) is reset to "0", the SSTB1 output goes to "L", or the SSTB1 output goes to "H". At the end of transmit/receive operation, when the data of the serial I/O1 register is all output from SOUT1, pulses are output in the period of 1 cycle of the transfer clock so as to cause the SSTB1 output to go "H" or the SSTB1 output to go "L". After that, each pulse is returned to the initial status in which SSTB1 output goes to "L" or the SSTB1 output goes to "H". Furthermore, after 1 cycle, the serial transfer status flag (b5) is reset to "0". In the automatic transfer serial I/O mode, whether the SSTB1 output is to be active at an end of each 1-byte data or after completion of transfer of all data can be selected by the SBUSY1 output * SSTB1 output function selection bit (b4 of address 001A16) of serial I/O1 control register 2. 2. SBUSY1 input signal The SBUSY1 input is a signal which receives a request for a stop of transmission/reception from the serial transfer destination. When the internal synchronous clock is selected, input an "H" level signal into the SBUSY1 input and an "L" level signal into the SBUSY1 input in the initial status in which transfer is stopped. When starting a transmit/receive operation, input an "L" level signal into the SBUSY1 input and an "H" level signal into the SBUSY1 input in the period of 1.5 cycles or more of the transfer clock. Then, transfer clocks are output from the SCLK1 output. When an "H" level signal is input into the SBUSY1 input and an "L" level signal into the SBUSY1 input after a transmit/receive operation is started, this transmit/receive operation are not stopped immediately and the transfer clocks from the SCLK1 output is not stopped until the specified number of bits are transmitted and received. The handshake unit of the 8-bit serial I/O is 8 bits and that of the automatic transfer serial I/O is 8 bits. When the external synchronous clock is selected, input an "H" level signal into the SBUSY1 input and an "L" level signal into the SBUSY1 input in the initial status in which transfer is stopped. At this time, the transfer clocks to be input in SCLK1 become invalid. During serial transfer, the transfer clocks to be input in SCLK1 become valid, enabling a transmit/receive operation, while an "L" level signal is input into the SBUSY1 input and an "H" level signal is input into the SBUSY1 input. When changing the input values in the SBUSY1 input and the SBUSY1 input at these operations, change them when the SCLK1 input is in a high state. When the high impedance of the SOUT1 output is selected by the SOUT1 pin control bit (b6), the SOUT1 output becomes active, enabling serial transfer by inputting a transfer clock to SCLK1, while an "L" level signal is input into the SBUSY1 input and an "H" level signal is input into the SBUSY1 input.
SSTB1
Serial transfer status flag
SCLK1
SOUT1
Fig. 26 SSTB1 output operation
SBUSY1
SCLK1
SOUT1
Fig. 27 SBUSY1 input operation (internal synchronous clock)
SBUSY1
SCLK1 Invalid SOUT1
(Output high-impedance)
Fig. 28 SBUSY1 input operation (external synchronous clock)
3. SBUSY1 output signal The SBUSY1 output is a signal which requests a stop of transmission/reception to the serial transfer destination. In the automatic transfer serial I/O mode, regardless of the internal or external synchronous clock, whether the SBUSY1 output is to be active at transfer of each 1-byte data or during transfer of all data can be selected by the SBUSY1 output * SSTB1 output function selection bit (b4). In the initial status, the status in which the serial I/O initialization bit (b4) is reset to "0", the SBUSY1 output goes to "H" and the SBUSY1 output goes to "L".
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FUNCTIONAL DESCRIPTION
When the internal synchronous clock is selected, in the 8-bit serial I/O mode and the automatic transfer serial I/O mode (SBUSY1 output function outputs in 1-byte units), the SBUSY1 output goes to "L" and the SBUSY1 output goes to "H" before 0.5 cycle (transfer clock) of the timing at which the transfer clock from the SCLK1 output goes to "L" at a start of transmit/receive operation. In the automatic transfer serial I/O mode (the SBUSY1 output function outputs all transfer data), the SBUSY1 output goes to "L" and the SBUSY1 output goes to "H" when the first transmit data is written into the serial I/O1 register (address 001B16). When the external synchronous clock is selected, the SBUSY1 output goes to "L" and the SBUSY1 output goes to "H" when transmit data is written into the serial I/O1 register to start a transmit operation, regardless of the serial I/O transfer mode. At termination of transmit/receive operation, the SBUSY1 output returns to "H" and the SBUSY1 output returns to "L", the initial status, when the serial transfer status flag is set to "0", regardless of whether the internal or external synchronous clock is selected. Furthermore, in the automatic transfer serial I/O mode (SBUSY1 output function outputs in 1-byte units), the SBUSY1 output goes to "H" and the SBUSY1 output goes to "L" each time 1-byte of receive data is written into the automatic transfer RAM.
SBUSY1
Serial transfer status flag
SBUSY1
Serial transfer status flag
SCLK1
SCLK1
Write to Serial I/O1 register Fig. 30 SBUSY1 output operation (external synchronous clock, 8-bit serial I/O)
SOUT1
Fig. 29 SBUSY1 output operation (internal synchronous clock, 8-bit serial I/O)
Automatic transfer interval SCLK1
Serial I/O1 register Automatic transfer RAM Automatic transfer RAM Serial I/O1 register
SBUSY1
Serial transfer status flag
SOUT1
Fig. 31 SBUSY1 output operation in automatic transfer serial I/O mode (internal synchronous clock, SBUSY1 output function outputs each 1-byte)
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FUNCTIONAL DESCRIPTION
4. SRDY1 output signal The SRDY1 output is a transmit/receive enable signal which informs the serial transfer destination that transmit/receive is ready. In the initial status, when the serial I/O initialization bit (b4) is reset to "0", the SRDY1 output goes to "L" and the SRDY1 output goes to "H". After transmitted data is stored in the serial I/O1 register (address 001B16) and a transmit/receive operation becomes ready, the SRDY1 output goes to "H" and the SRDY1 output goes to "L". When a transmit/receive operation is started and the transfer clock goes to "L", the SRDY1 output goes to "L" and the SRDY1 output goes to "H". 5. SRDY1 input signal The SRDY1 input signal becomes valid only when the SRDY1 input and the SBUSY1 output are used. The SRDY1 input is a signal for receiving a transmit/receive ready completion signal from the serial transfer destination. When the internal synchronous clock is selected, input a low level signal into the SRDY1 input and a high level signal into the SRDY1 input in the initial status in which the transfer is stopped. When an "H" level signal is input into the SRDY1 input and an "L" level signal is input into the SRDY1 input for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the SCLK1 output and a transmit/receive operation is started. After the transmit/receive operation is started and an "L" level signal is input into the SRDY1 input and an "H" level signal into the SRDY1 input, this operation cannot be immediately stopped. After the specified number of bits are transmitted and received, the transfer clocks from the SCLK1 output is stopped. The handshake unit of the 8-bit serial I/O and that of the automatic transfer serial I/O are of 8 bits. When the external synchronous clock is selected, the SRDY1 input becomes one of the triggers to output the SBUSY1 signal. To start a transmit/receive operation (SBUSY1 output: "L", SBUSY1 output: "H"), input an "H" level signal into the SRDY1 input and an "L" level signal into the SRDY1 input, and also write transmit data into the serial I/O1 register.
SRDY1
SCLK1
Write to serial I/O1 register
Fig. 32 SRDY1 output operation
SRDY1
SCLK1
SOUT1
Fig. 33 SRDY1 input operation (internal synchronous clock)
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SCLK1 SRDY1 SBUSY1
SCLK1 SRDY1 SBUSY1
A:
Write to serial I/O1 register
SRDY1
SBUSY1
A:
Internal synchronous clock selection
B:
External synchronous clock selection
SCLK1
B:
Write to serial I/O1 register
Fig. 34 Handshake operation at serial I/O1 mutual connecting (1)
SCLK1 SRDY1 SBUSY1
SCLK1 SRDY1 SBUSY1
A:
Write to serial I/O1 register
SRDY1
SBUSY1
A:
Internal synchronous clock selection
B:
External synchronous clock selection
SCLK1
B:
Write to serial I/O1 register
Fig. 35 Handshake operation at serial I/O1 mutual connecting (2)
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FUNCTIONAL DESCRIPTION
Serial I/O2
Serial I/O2 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation during serial I/O2 operation. register (address 001D16) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock for serial I/O2 operation. If an internal clock is used, transmit/receive is started by a write signal to the serial I/O2 transmit/receive buffer register (TB/RB) (address 001F16). When P67 (SCLK22) is selected as a clock I/O pin, SRDY2 output function is invalid, and P66 (SCLK21) is used as an I/O port.
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode can be selected by setting the serial I/O2 mode selection bit (b6) of the serial I/O2 control
Data bus Address 001F16 Receive buffer register P64/RXD
"0 "
Serial I/O2 control register
Address 001D16
Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit
Receive shift register Shift clock Serial I/O2 clock I/O pin selection bit
"1 " "0 "
P66/SCLK21 P67/SRDY2/SCLK22 XIN
Internal system clock selection bit Serial I/O2 synchronous clock selection bit
"0 "
"1 "
XCIN
1/2
"1 "
BRG count source selection bit Division ratio 1/(n+1) Baud rate generator BRG clock Address 003716 1/4 switch bit Falling edge detector Shift clock Transmit shift register Transmit buffer register Address 001F16 Data bus Clock control circuit
1/4
P67/SRDY2/SCLK22
F/F Serial I/O2 clock I/O pin selection bit
P65/TXD
Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O2 status register Address 001E16
Fig. 36 Block diagram of clock synchronous serial I/O2
Transmit/Receive shift clock (1/2 to 1/2048 of internal clock or external clock) Serial I/O2 output TxD Serial I/O2 input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Receive enable signal SRDY2 Write-in signal to serial I/O2 transmit/receive buffer register (address 001F16) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection
TBE = 1 TSC = 0
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O2 control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1".
Fig. 37 Operation of clock synchronous serial I/O2 function
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FUNCTIONAL DESCRIPTION
(2) Asynchronous serial I/O (UART) mode
The asynchronous serial I/O (UART) mode can be selected by clearing the serial I/O2 mode selection bit (b6) of the serial I/O2 control register (address 001D16) to "0". Eight serial data transfer formats can be selected and the transfer formats used by the transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer (the two buffers have the same address in memory). Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can receive 2-byte data continuously.
Data bus Address 001F16 OE P64/RXD Receive buffer register Serial I/O2 control register Address 001D16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 PE FE P66/SCLK21 P67/SRDY2/SCLK22 XIN
"1" "0" SP detector
Character length selection bit 7 bit ST detector Receive shift register 8 bit
Serial I/O2 clock I/O pin selection bit
Clock control circuit Serial I/O2 synchronous clock selection bit
UART control register Address 003816
"1"
Internal system clock selection bit
"0 "
BRG count source selection bit
XCIN
1/2
"1 "
BRG clock switch bit
1/4
Division ratio 1/(n+1) Baud rate generator Address 003716 Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Address 001E16 Serial I/O2 status register
ST/SP/PA generator
1/16 P65/TXD Character length selection bit Transmit buffer register Address 001F16 Data bus Transmit shift register
Fig. 38 Block diagram of UART serial I/O2
Transmit or receive clock Write-in signal to transmit buffer register
TBE=0 TSC=0 TBE=1 TBE=0 TBE=1 ST D0 D1 D0 D1 TSC=1* SP
Serial I/O2 output TXD
SP
ST
Read-out signal from receive buffer register
1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit
RBF=1 ST D0 D1 SP ST D0 RBF=0 D1
* Generated at 2nd bit in 2-stop bit mode
RBF=1
Serial I/O2 input RXD
SP
Fig. 39 Operation of UART serial I/O2 function
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FUNCTIONAL DESCRIPTION
[Serial I/O2 Control Register] SIO2CON (001D16)
The serial I/O2 control register contains eight control bits for serial I/O2 functions.
[UART Control Register] UARTCON (003816)
This is a 7 bit register containing four control bits, of which four bits are valid when UART is selected, and of which three bits are always valid. Data format of serial data receive/transfer and the output structure of the P65/TxD pin and others are set by this register.
[Serial I/O2 Status Register] SIO2STS (001E16)
The read-only serial I/O2 status register consists of seven flags (b0 to b6) which indicate the operating status of the serial I/O2 function and various errors. Three of the flags (b4 to b6) are only valid in the UART mode. The receive buffer full flag (b1) is cleared to "0" when the receive buffer is read. The error detection is performed at the same time data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A writing to the serial I/O2 status register clears error flags OE, PE, FE, and SE (b3 to b6, respectively). Writing "0" to the serial I/O2 enable bit (SIOE : b7 of the serial I/O2 control register) also clears all the status flags, including the error flags. All bits of the serial I/O2 status register are initialized to "0" at reset, but if the transmit enable bit (b4) of the serial I/O2 control register has been set to "1", the transmit shift register shift completion flag (b2) and the transmit buffer empty flag (b0) become "1".
[Serial I/O2 Transmit Buffer Register/Receive Buffer Register] TB/RB (001F16)
The transmit buffer and the receive buffer are located in the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0".
[Baud Rate Generator] BRG (003716)
The baud rate generator determines the baud rate for serial transfer. With the 8-bit counter having a reload register, the baud rate generator divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator.
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FUNCTIONAL DESCRIPTION
b7 b0
Serial I/O2 status register (SIO2STS : address 001E16) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read)
b7
b0
Serial I/O2 control register (SIO2CON : address 001D16) BRG count source selection bit (CSS) 0: f(XIN) or f(XCIN)/2 or f(XCIN) 1: f(XIN)/4 or f(XCIN)/8 or f(XCIN)/4 Serial I/O2 synchronous clock selection bit (SCS) 0: BRG/ 4 (when clock synchronous serial I/O is selected) BRG/16 (UART is selected) 1: External clock input (when clock synchronous serial I/O is selected) External clock input/16 (UART is selected) SRDY2 output enable bit (SRDY) 0: P67 pin operates as ordinary I/O pin 1: P67 pin operates as SRDY2 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O2 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O2 enable bit (SIOE) 0: Serial I/O2 disabled (pins P64 to P67 operate as ordinary I/O pins) 1: Serial I/O2 enabled (pins P64 to P67 operate as serial I/O pins)
b7
b0
UART control register (UARTCON : address 003816) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P65/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) BRG clock switch bit 0: XIN or XCIN (depends on internal system clock) 1: XCIN Serial I/O2 clock I/O pin selection bit 0: SCLK21 (P67/SCLK22 pin is used as I/O port or SRDY2 output pin.) 1: SCLK22 (P66/SCLK21 pin is used as I/O port.) Not used (return "1" when read)
Fig. 40 Structure of serial I/O2 related register sNotes When setting the transmit enable bit to "1", the serial I/O2 transmit interrupt request bit is automatically set to "1". When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. Set the serial I/O1 transmit interrupt enable bit to "0" (disabled). Set the transmit enable bit to "1". Set the serial I/O1 transmit interrupt request bit to "0" after 1 or more instructions have been executed. Set the serial I/O1 tranmit interrupt enable bit to "1" (enabled).
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HARDWARE
FUNCTIONAL DESCRIPTION
Serial I/O3
The serial I/O3 function can be used only for 8-bit clock synchronous serial I/O. All serial I/O pins are shared with port P9, which can be set with the serial I/O3 control register (address 0EEC16).
b7 b0
Serial I/O3 control register (SIO3CON : address 0EEC16) Internal synchronous clock selection bits
b2 b1 b0
[Serial I/O3 Control Register (SIO3CON)] 0EEC16
The serial I/O3 control register contains eight bits which control various serial I/O functions. q Serial I/O3 Operation Either the internal clock or external clock can be selected as synchronous clock for serial I/O3 transfer. The internal clock can use a built-in dedicated divider where 6 different clocks are selected. In the case of the internal clock used, transfer is started by a write signal to the serial I/O3 register (address 0EED16). When 8-bit data has been transferred, the SOUT3 pin goes to high impedance state. In the case of the external clock used, the clock must be externally controlled. It is because the contents of serial I/O3 register is kept shifted while the clock is being input. Additionally, the function to put the SOUT3 pin high impedance state at completion of data transfer is not available. The serial I/O3 interrupt request bit is set at completion of 8-bit data transfer, regardless of use of the internal clock or external clock.
0 0 0: f(XIN)/4 (f(XCIN)/8) 0 0 1: f(XIN)/8 (f(XCIN)/16) 0 1 0: f(XIN)/16 (f(XCIN)/32) 0 1 1: f(XIN)/32 (f(XCIN)/64) 1 1 0: f(XIN)/64 (f(XCIN)/128) 1 1 1: f(XIN)/128 (f(XCIN)/256) Serial I/O3 port selection bit (P91, P92) 0: I/O port 1: SOUT3, SCLK3 signal output SRDY3 output selection bit (P93) 0: I/O port 1: SRDY3 signal output Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O3 synchronous clock selection bit 0: External clock 1: Internal clock P91/SOUT3 P-channel output disable bit (P91) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode)
Fig. 42 Structure of serial I/O3 control register
XCIN
1/2 "1"
Internal system clock selection bit
1/4 1/8
Internal synchronous clock selection bits
XIN
"0 "
Divider
1/16 1/32 1/64 1/128
Data bus
P93 latch
"0 "
P93/SRDY3
Serial I/O3 synchronous clock selection bit "1" SRDY3 Synchronization
SCLK3
"1 " circuit SRDY3 output selection bit External clock
"0"
P92 latch
"0 "
P92/SCLK3
"1 " Serial I/O3 port selection bit
Serial I/O3 counter (3)
Serial I/O3 interrupt request
P91 latch
"0 "
P91/SOUT3
"1 " Serial I/O3 port selection bit
P90/SIN3
Serial I/O3 shift register (8)
Fig. 41 Block diagram of serial I/O3
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FUNCTIONAL DESCRIPTION
Synchronous clock
Transfer clock
Serial I/O3 register write signal
(Note)
Serial I/O3 output SOUT3
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O3 input SIN3
Receive enable signal SRDY3
Note: When the internal clock is selected as the transfer clock, the SOUT3 pin goes to high impedance after transfer completion.
Serial I/O3 interrupt request bit set
Fig. 43 Timing of serial I/O3 (LSB first)
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HARDWARE
FUNCTIONAL DESCRIPTION
FLD CONTROLLER
The M38B7 group has fluorescent display (FLD) drive and control circuits. Table 9 shows the FLD controller specifications.
Table 9 FLD controller specifications Item High-breakdownvoltage output port CMOS port Specifications * 52 pins (20 pins can be switched to general-purpose ports) * 4 pins (all 4 pins can be switched to general-purpose ports) (A driver IC must be installed externally) * Used FLD output 28 segment 28 digit (segment number + digit number 56) * Used digit output 40 segment 16 digit (segment number 40, digit number 16) * Connected to M35501 56 segment (connected number of M35501) digit (segment number 56, digit number number of M35501 16) * Used P64 to P67 expansion 52 segment 16 digit (segment number 52, digit number 16) * 4.0 s to 1024 s (count source XIN/16, 4 MHz) * 16.0 s to 4096 s (count source XIN/64, 4 MHz) * 4.0 s to 1024 s (count source XIN/16, 4 MHz) * 16.0 s to 4096 s (count source XIN/64, 4 MHz) * Digit interrupt * FLD blanking interrupt * Key-scan using digit * Key-scan using segment * Digit pulse output function This function automatically outputs digit pulses. * M35501 connection function The number of digits can be increased easily by using the output of DIMOUT(P73) as CLK for the M35501. * Toff section generating/nothing function This function does not generate Toff1 section when the connected outputs are the same. * Gradation display function This function allows each segment to be set for dark or bright display. * P64 to P67 expansion function This function provides 16 lines of digit outputs from four ports by attaching the decoder converting 4-bit data to 16-bit data.
FLD controller port
Display pixel number
Period Dimmer time Interrupt Key-scan Expanded function
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FUNCTIONAL DESCRIPTION
Main address bus
Main data bus
Local data bus
Digit output set switch register P20/FLD0 DIG/FLD P21/FLD1 DIG/FLD P22/FLD2 DIG/FLD P23/FLD3 DIG/FLD 8 P24/FLD4 DIG/FLD P25/FLD5 DIG/FLD P26/FLD6 DIG/FLD P27/FLD7 DIG/FLD 0EF316 000416 P00/FLD8 P01/FLD9 P02/FLD10 P03/FLD11 P04/FLD12 P05/FLD13 P06/FLD14 P07/FLD15 000016 DIG/FLD DIG/FLD DIG/FLD DIG/FLD 8 DIG/FLD DIG/FLD DIG/FLD DIG/FLD 0EF216
0E0016 FLD automatic display RAM
Local address bus
0EDF16
P10/FLD16 P11/FLD17 P12/FLD18 P13/FLD19 8 P14/FLD20 P15/FLD21 P16/FLD22 P17/FLD23 000216 P30/FLD24 P31/FLD25 P32/FLD26 P33/FLD27 8 P34/FLD28 P35/FLD29 P36/FLD30 P37/FLD31 000616
FLDC mode register (0EF416)
FLD data pointer reload register (0EF816)
FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P 0EF916
P40/FLD32 P41/FLD33 P42/FLD34 P43/FLD35 8 P44/FLD36 P45/FLD37 P46/FLD38 P47/FLD39 000816
Address decoder
FLD data pointer (0EF816)
Timing generator
FLD/P P50/FLD40 FLD/P P51/FLD41 FLD/P P52/FLD42 FLD/P P53/FLD43 8 FLD/P P54/FLD44 FLD/P P55/FLD45 FLD/P P56/FLD46 FLD/P P57/FLD47 000A16 0EFA16 FLD blanking interrupt FLD digit interrupt FLD/P P60/FLD48 FLD/P P61/FLD49 FLD/P P62/FLD50 FLD/P P63/FLD51 8 FLD/P P64/FLD52 FLD/P P65/FLD53 FLD/P P66/FLD54 FLD/P P67/FLD55 000C16 0EFB16 FLD/Port switch register
Fig. 44 Block diagram of FLD control circuit
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HARDWARE
FUNCTIONAL DESCRIPTION
b7 b6 b5 b4 b3 b2 b1 b0
FLDC mode register (FLDM: address 0EF416) Automatic display control bit 0 : General-purpose mode 1 : Automatic display mode Display start bit 0 : Stop display 1 : Display( start to display by switching "0" to "1") Tscan control bits
b3b2
0 0 : FLD digit interrupt (at rising edge of each digit) 0 1 : 1 Tdisp 1 0 : 2 Tdisp FLD blanking interrupt 1 1 : 3 Tdisp (at falling edge of the last digit) Timing number control bit 0 : 16 timing mode 1 : 32 timing mode Gradation display mode selection control bit 0 : Not selecting 1 : Selecting (Note) Tdisp counter count source selection bit 0 : f(XIN)/16 1 : f(XIN)/64 High-breakdown voltage port drivability selection bit 0 : Drivability strong 1 : Drivability weak Note: When the gradation display mode is selected, the max. number of timing is 16 timing. (Be sure to set the timing number control bit to "0".)
b7 b6 b5 b4 b3 b2 b1 b0
FLD output control register (FLDCON: address 0EFC16) P64 to P67 output reverse bit 0 : Output normally 1 : Reverse output Not used (return "0" when read); (Do not write "1".) P64 to P67 Toff invalid bit 0 : Operation normally 1 : Toff invalid Not used (return "0" when read); (Do not write "1".) P73 dimmer output control bit 0 : Normal port 1 : Dimmer output Generating/Not of CMOS port Toff section selection bit 0 : Toff section not generated 1 : Toff section generated Generating/Not of high-breakdown voltage port Toff section selection bit 0 : Toff section not generated 1 : Toff section generated Toff2 SET/RESET switch bit 0 : Toff2 RESET; Toff1 SET 1 : Toff2 SET; Tdisp RESET
Fig. 45 Structure of FLDC related registers (1)
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FUNCTIONAL DESCRIPTION
b7 b6 b5 b4 b3 b2 b1 b0
Port P4 FLD/Port switch register (P4FPR: address 0EF916) Port P40 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P41 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P42 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P43 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P44 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P45 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P46 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P47 FLD/Port switch bit 0 : Normal port 1 : FLD output port
b7 b6 b5 b4 b3 b2 b1 b0
Port P5 FLD/Port switch register (P5FPR: address 0EFA16) Port P50 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P51 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P52 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P53 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P54 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P55 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P56 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P57 FLD/Port switch bit 0 : Normal port 1 : FLD output port
Fig. 46 Structure of FLDC related registers (2)
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FUNCTIONAL DESCRIPTION
b7 b6 b5 b4 b3 b2 b1 b0
Port P6 FLD/Port switch register (P6FPR: address 0EFB16) Port P60 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P61 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P62 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P63 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P64 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P65 FLD/Port switch bit 0 : Normal port 1 : FLD output port Port P66 FLD/Port switch bit 0 : Normal port 1 : FLD output Port Port P67 FLD/Port switch bit 0 : Normal port 1 : FLD output port
Fig. 47 Structure of FLDC related registers (3)
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FUNCTIONAL DESCRIPTION
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 digit output set switch register (P0DOR: address 0EF216) Port P00 FLD/Digit switch bit 0 : FLD output 1 : Digit output Port P01 FLD/Digit switch bit 0 : FLD output 1 : Digit output Port P02 FLD/Digit switch bit 0 : FLD output 1 : Digit output Port P03 FLD/Digit switch bit 0 : FLD output 1 : Digit output Port P04 FLD/Digit switch bit 0 : FLD output 1 : Digit output Port P05 FLD/Digit switch bit 0 : FLD output 1 : Digit output Port P06 FLD/Digit switch bit 0 : FLD output 1 : Digit output Port P07 FLD/Digit switch bit 0 : FLD output 1 : Digit output
b7 b6 b5 b4 b3 b2 b1 b0
Port P2 digit output set switch register (P2DOR: address 0EF316) Port P20 FLD/Digit switch bit 0 : FLD output 1 : Digit output Port P21 FLD/Digit switch bit 0 : FLD output 1 : Digit output Port P22 FLD/Digit switch bit 0 : FLD output 1 : Digit output Port P23 FLD/Digit switch bit 0 : FLD output 1 : Digit output Port P24 FLD/Digit switch bit 0 : FLD output 1 : Digit output Port P25 FLD/Digit switch bit 0 : FLD output 1 : Digit output Port P26 FLD/Digit switch bit 0 : FLD output 1 : Digit output Port P27 FLD/Digit switch bit 0 : FLD output 1 : Digit output
Fig. 48 Structure of FLDC related registers (4)
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FUNCTIONAL DESCRIPTION
FLD Automatic Display Pins
P0 to P6 are the pins capable of automatic display output for the FLD. The FLD star ts operating by setting the automatic display control bit (bit 0 at address 0EF416) to "1". There is the FLD output function that outputs the RAM contents from the port every timing or the digit output function that drives the port high with a digit timing. The FLD can be displayed using the FLD output for the segments and the digit or FLD output for the digits. When using the FLD output for the digits, be sure to write digit display patterns to the RAM in advance. The remaining segment and digit lines can be used as general-purpose ports. Settings of each port are shown below.
Table 10 Pins in FLD automatic display mode Automatic display pin Setting method Port FLD0 to FLD15 The individual bits of the digit output set switch registers (addresses 0EF216, 0EF316) can P0, P2 set each pin to either an FLD port ("0") or a digit port ("1"). When the pins are set for the digit port, the digit pulse output function is enabled, so that the digit pulses can always be output regardless the value of FLD automatic display RAM. Setting the automatic display control bit (bit 0 of address 0EF416) to "1" can set these ports to the FLD exclusive use port. The individual bits of the FLD/Port switch register (addresses 0EF916 to 0EFB16) can set each pin to either an FLD port ("1") or a general-purpose port ("0"). The individual bits of the port P6 FLD/Port switch register (address 0EFB16) can set each pin to either FLD port ("1") or general-purpose port ("0"). A variety of output pulses can be available by setting of the FLD output control register (address 0EFC16). The port output structure is the CMOS output. When using the port as a display pin, a driver IC must be installed externally.
P1, P3 P4, P5, P60 to P63 P64 to P67
FLD16 to FLD31 FLD32 to FLD51 FLD52 to FLD55
Setting example 1 This is a register setup example where only FLD output is used. In this case, the digit display output pattern must be set in the FLD automatic display RAM in advance.
Number of segments Number of digits
Setting example 2 This is a register setup example where both FLD output and digit waveform output are used. In this case, because the digit display output is automatically generated, there is no need to set the display pattern in the FLD automatic display RAM.
Number of segments Number of digits
36 16
The contents of digit output set switch registers (0EF216, 0EF316)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28 12
The contents of digit output set switch registers (0EF216, 0EF316)
1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
Port P2
FLD0 (DIG output) FLD1 (DIG output) FLD2 (DIG output) FLD3 (DIG output) FLD4 (DIG output) FLD5 (DIG output) FLD6 (DIG output) FLD7 (DIG output) FLD8 (DIG output) FLD9 (DIG output) FLD10 (DIG output) FLD11 (DIG output) FLD12 (DIG output) FLD13 (DIG output) FLD14 (DIG output) FLD15 (DIG output) FLD16 (SEG output) FLD17 (SEG output) FLD18 (SEG output) FLD19 (SEG output) FLD20 (SEG output) FLD21 (SEG output) FLD22 (SEG output) FLD23 (SEG output) FLD24 (SEG output) FLD25 (SEG output) FLD26 (SEG output) FLD27 (SEG output) FLD28 (SEG output) FLD29 (SEG output) FLD30 (SEG output) FLD31 (SEG output)
Port P2
FLD/Port switch registers (0EF916 to 0EFB16)
FLD0 (DIG output) FLD1 (DIG output) FLD2 (DIG output) FLD3 (DIG output) FLD4 (DIG output) FLD5 (DIG output) FLD6 (DIG output) FLD7 (DIG output) FLD8 (DIG output) FLD9 (DIG output) FLD10 (DIG output) FLD11 (DIG output) FLD12 (SEG output) FLD13 (SEG output) FLD14 (SEG output) FLD15 (SEG output) FLD16 (SEG output) FLD17 (SEG output) FLD18 (SEG output) FLD19 (SEG output) FLD20 (SEG output) FLD21 (SEG output) FLD22 (SEG output) FLD23 (SEG output) FLD24 (SEG output) FLD25 (SEG output) FLD26 (SEG output) FLD27 (SEG output) FLD28 (SEG output) FLD29 (SEG output) FLD30 (SEG output) FLD31 (SEG output)
FLD/Port switch registers (0EF916 to 0EFB16)
Port P0
Port P4
1 1 1 1 1 1 1 1
FLD32 (SEG output) FLD33 (SEG output) FLD34 (SEG output) FLD35 (SEG output) FLD36 (SEG output) FLD37 (SEG output) FLD38 (SEG output) FLD39(SEG output)
Port P0
Port P4
1 1 1 1 1
FLD32 (SEG output) FLD33 (SEG output) FLD34 (SEG output) FLD35 (SEG output) FLD36 (SEG output) 1 FLD37 (SEG output) 1 FLD38 (SEG output) 1 FLD39 (SEG output) 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 FLD40 (SEG output) FLD41 (SEG output) FLD42 (SEG output) FLD43 (SEG output) FLD44 (port output) FLD45 (port output) FLD46 (port output) FLD47 (port output) FLD48 (port output) FLD49 (port output) FLD50 (port output) FLD51 (port output) FLD52 (port output)
Port P1
Port P5
1 FLD40 (SEG output) 1 FLD41 (SEG output) 1 FLD42 (SEG output) 1 FLD43 (SEG output) 1 FLD44 (SEG output) 1 FLD45 (SEG output) 1 FLD46 (SEG output) 1 FLD47 (SEG output) 1 1 1 1 0 0 0 0 FLD48 (SEG output) FLD49 (SEG output) FLD50 (SEG output) FLD51 (SEG output) FLD52 (port output) FLD53 (port output) FLD54 (port output) FLD55 (port output)
Port P1
Port P5
Port P3
Port P6
Port P3
Port P6
FLD53 (port output) FLD54 (port output) 0 FLD55 (port output)
DIG output : This output is connected to digit of the FLD. SEG output : This output is connected to segment of the FLD. Port output : This output is general-purpose port (used by program).
DIG output : This output is connected to digit of the FLD. SEG output : This output is connected to segment of the FLD. Port output : This output is general-purpose port (used by program).
Fig. 49 Segment/Digit setting example
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FUNCTIONAL DESCRIPTION
FLD Automatic Display RAM
The FLD automatic display RAM uses the 224 bytes of addresses 0E0016 to 0EDF16. For FLD, the 3 modes of 16-timing*ordinary mode, 16-timing*gradation display mode and 32-timing mode are available depending on the number of timings and the use/not use of gradation display. The automatic display RAM in each mode is as follows:
(3) 32-timing mode
This mode is used when the display timing is 16 or greater. This mode can be used for up to 32-timing. The 224 bytes of addresses 0E0016 to 0EDF16 are used as an FLD display data store area. The FLD data pointer (address 0EF816) is a register to count display timings. This pointer has a reload register. When the pointer underflow occurs, it starts counting over again after being reloaded with the initial value in the reload register. Make sure that (the timing counts - 1) is set to the FLD data pointer. When writing data to this address, the data is written to the FLD data pointer reload register; when reading data from this address, the value in the FLD data pointer is read.
(1) 16-timing*ordinary mode
This mode is used when the display timing is 16 or less. The 112 bytes of addresses 0E7016 to 0EDF16 are used as a FLD display data store area. Because addresses 0E0016 to 0E6F16 are not used as the automatic display RAM, they can be the ordinary RAM.
(2) 16-timing*gradation display mode
This mode is used when the display timing is 16 or less, in which mode each segment can be set for dark or bright display. The 224 bytes of addresses 0E0016 to 0EDF16 are used. The 112 bytes of addresses 0E7016 to 0EDF16 are used as an FLD display data store area, while the 112 bytes of addresses 0E0016 to 0E6F16 are used as a gradation display control data store area.
16-timing*ordinary mode 0E0016
Not used
16-timing*gradation display mode 0E0016
Gradation display control data stored area
32-timing mode
0E0016
0E7016
1 to 16 timing display data stored area
0E7016
1 to 16 timing display data stored area
1 to 32 timing display data stored area
0EDF16
0EDF16
0EDF16
Fig. 50 FLD automatic display RAM assignment
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FUNCTIONAL DESCRIPTION
Data Setup (1) 16-timing*ordinary mode
The area of addresses 0E7016 to 0EDF16 are used as a FLD automatic display RAM. When data is stored in the FLD automatic display RAM, the last data of FLD port P6 is stored at address 0E7016, the last data of FLD port P5 is stored at address 0E8016, the last data of FLD port P4 is stored at address 0E9016, the last data of FLD port P3 is stored at address 0EA016, the last data of FLD port P1 is stored at address 0EB016, the last data of FLD port P0 is stored at address 0EC016, and the last data of FLD port P2 is stored at address 0ED016, to assign in sequence from the last data respectively. The first data of the FLD port P6, P5, P4, P3, P1, P0, and P2 is stored at an address which adds the value of (the timing number - 1) to the corresponding addresses 0E7016, 0E8016, 0E9016, 0EA016, 0EB016, 0EC016 and 0ED016. Set the FLD data pointer reload register to the value given by (the timing number - 1).
(2) 16-timing*gradation display mode
Display data setting is performed in the same way as that of the 16-timing*ordinary mode. Gradation display control data is arranged at an address resulting from subtracting 007016 from the display data store address of each timing and pin. Bright display is performed by setting "0", and dark display is performed by setting "1" .
(3) 32-timing Mode
The area of addresses 0E0016 to 0EDF16 is used as a FLD automatic display RAM. When data is stored in the FLD automatic display RAM, the last data of FLD port P6 is stored at address 0E0016, the last data of FLD port P5 is stored at address 0E2016, the last data of FLD port P4 is stored at address 0E4016, the last data of FLD port P3 is stored at address 0E6016, the last data of FLD port P1 is stored at address 0E8016, the last data of FLD port P0 is stored at address 0EA016, and the last data of FLD port P2 is stored at address 0EC016, to assign in sequence from the last data respectively. The first data of the FLD port P6, P5, P4, P3, P1, P0, and P2 is stored at an address which adds the value of (the timing number - 1) to the corresponding addresses 0E0016, 0E2016, 0E4016, 0E6016, 0E8016, 0EA016 and 0EC016. Set the FLD data pointer reload register to the value given by (the timing number - 1).
Number of timing: 8 (FLD data pointer reload register = 7)
B it Address
7
6
5
4
3
2
1
0
Bit Address
7
6
5
4
3
2
1
0
0E7016 0E7116 0E7216 0E7316 0E7416 0E7516 0E7616 0E7716 0E7816 0E7916 0E7A16 0E7B16 0E7C16 0E7D16 0E7E16 0E7F16 0E8016 0E8116 0E8216 0E8316 0E8416 0E8516 0E8616 0E8716 0E8816 0E8916 0E8A16 0E8B16 0E8C16 0E8D16 0E8E16 0E8F16 0E9016 0E9116 0E9216 0E9316 0E9416 0E9516 0E9616 0E9716 0E9816 0E9916 0E9A16 0E9B16 0E9C16 0E9D16 0E9E16 0E9F16 0EA016 0EA116 0EA216 0EA316 0EA416 0EA516 0EA616 0EA716 0EA816 0EA916 0EAA16 0EAB16 0EAC16 0EAD16 0EAE16 0EAF16
The last timing (The last data of FLDP6)
Timing for start (The first data of FLDP6) FLDP6 data area
The last timing (The last data of FLDP5)
Timing for start (The first data of FLDP5) FLDP5 data area
The last timing (The last data of FLDP4)
Timing for start (The first data of FLDP4) FLDP4 data area
0EB016 0EB116 0EB216 0EB316 0EB416 0EB516 0EB616 0EB716 0EB816 0EB916 0EBA16 0EBB16 0EBC16 0EBD16 0EBE16 0EBF16 0EC016 0EC116 0EC216 0EC316 0EC416 0EC516 0EC616 0EC716 0EC816 0EC916 0ECA16 0ECB16 0ECC16 0ECD16 0ECE16 0ECF16 0ED016 0ED116 0ED216 0ED316 0ED416 0ED516 0ED616 0ED716 0ED816 0ED916 0EDA16 0EDB16 0EDC16 0EDD16 0EDE16 0EDF16
The last timing (The last data of FLDP1)
Timing for start (The first data of FLDP1) FLDP1 data area
The last timing (The last data of FLDP0)
Timing for start (The first data of FLDP0) FLDP0 data area
The last timing (The last data of FLDP2)
Timing for start (The first data of FLDP2) FLDP2 data area
The last timing (The last data of FLDP3)
Timing for start (The first data of FLDP3) FLDP3 data area
Fig. 51 Example of using FLD automatic display RAM in 16-timing*ordinary mode
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FUNCTIONAL DESCRIPTION
Number of timing: 15 (FLD data pointer reload register = 14)
B it Address
7
6
5
4
3
2
1
0
Bit Address
7
6
5
4
3
2
1
0
0E7016 0E7116 0E7216 0E7316 0E7416 0E7516 0E7616 0E7716 0E7816 0E7916 0E7A16 0E7B16 0E7C16 0E7D16 0E7E16 0E7F16 0E8016 0E8116 0E8216 0E8316 0E8416 0E8516 0E8616 0E8716 0E8816 0E8916 0E8A16 0E8B16 0E8C16 0E8D16 0E8E16 0E8F16 0E9016 0E9116 0E9216 0E9316 0E9416 0E9516 0E9616 0E9716 0E9816 0E9916 0E9A16 0E9B16 0E9C16 0E9D16 0E9E16 0E9F16 0EA016 0EA116 0EA216 0EA316 0EA416 0EA516 0EA616 0EA716 0EA816 0EA916 0EAA16 0EAB16 0EAC16 0EAD16 0EAE16 0EAF16 0EB016 0EB116 0EB216 0EB316 0EB416 0EB516 0EB616 0EB716 0EB816 0EB916 0EBA16 0EBB16 0EBC16 0EBD16 0EBE16 0EBF16 0EC016 0EC116 0EC216 0EC316 0EC416 0EC516 0EC616 0EC716 0EC816 0EC916 0ECA16 0ECB16 0ECC16 0ECD16 0ECE16 0ECF16 0ED016 0ED116 0ED216 0ED316 0ED416 0ED516 0ED616 0ED716 0ED816 0ED916 0EDA16 0EDB16 0EDC16 0EDD16 0EDE16 0EDF16
The last timing (The last data of FLDP6)
FLDP6 data area
Timing for start (The first data of FLDP6) The last timing (The last data of FLDP5)
FLDP5 data area
Timing for start (The first data of FLDP5) The last timing (The last data of FLDP4)
FLDP4 data area
Timing for start (The first data of FLDP4) The last timing (The last data of FLDP3)
FLDP3 data area
Timing for start (The first data of FLDP3) The last timing (The last data of FLDP1)
FLDP1 data area
Timing for start (The first data of FLDP1) The last timing (The last data of FLDP0)
FLDP0 data area
Timing for start (The first data of FLDP0) The last timing (The last data of FLDP2)
FLDP2 data area
Timing for start (The first data of FLDP2)
0E0016 0E0116 0E0216 0E0316 0E0416 0E0516 0E0616 0E0716 0E0816 0E0916 0E0A16 0E0B16 0E0C16 0E0D16 0E0E16 0E0F16 0E1016 0E1116 0E1216 0E1316 0E1416 0E1516 0E1616 0E1716 0E1816 0E1916 0E1A16 0E1B16 0E1C16 0E1D16 0E1E16 0E1F16 0E2016 0E2116 0E2216 0E2316 0E2416 0E2516 0E2616 0E2716 0E2816 0E2916 0E2A16 0E2B16 0E2C16 0E2D16 0E2E16 0E2F16 0E3016 0E3116 0E3216 0E3316 0E3416 0E3516 0E3616 0E3716 0E3816 0E3916 0E3A16 0E3B16 0E3C16 0E3D16 0E3E16 0E3F16 0E4016 0E4116 0E4216 0E4316 0E4416 0E4516 0E4616 0E4716 0E4816 0E4916 0E4A16 0E4B16 0E4C16 0E4D16 0E4E16 0E4F16 0E5016 0E5116 0E5216 0E5316 0E5416 0E5516 0E5616 0E5716 0E5816 0E5916 0E5A16 0E5B16 0E5C16 0E5D16 0E5E16 0E5F16 0E6016 0E6116 0E6216 0E6316 0E6416 0E6516 0E6616 0E6716 0E6816 0E6916 0E6A16 0E6B16 0E6C16 0E6D16 0E6E16 0E6F16
The last timing (The last data of FLDP6)
FLDP6 gradation display data area
Timing for start (The first data of FLDP6) The last timing (The last data of FLDP5)
FLDP5 gradation display data area
Timing for start (The first data of FLDP5) The last timing (The last data of FLDP4)
FLDP4 gradation display data area
Timing for start (The first data of FLDP4) The last timing (The last data of FLDP3)
FLDP3 gradation display data area
Timing for start (The first data of FLDP3) The last timing (The last data of FLDP1)
FLDP1 gradation display data area
Timing for start (The first data of FLDP1) The last timing (The last data of FLDP0)
FLDP0 gradation display data area
Timing for start (The first data of FLDP0) The last timing (The last data of FLDP2)
FLDP2 gradation display data area
Timing for start (The first data of FLDP2)
Fig. 52 Example of using FLD automatic display RAM in 16-timing*gradation display mode
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HARDWARE
FUNCTIONAL DESCRIPTION
Number of timing: 20 (FLD data pointer reload register = 19)
B it Address B it Address
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0E7016 0E7116 0E7216 0E7316 0E7416 0E7516 0E7616 0E7716 0E7816 0E7916 0E7A16 0E7B16 0E7C16 0E7D16 0E7E16 0E7F16 0E8016 0E8116 0E8216 0E8316 0E8416 0E8516 0E8616 0E8716 0E8816 0E8916 0E8A16 0E8B16 0E8C16 0E8D16 0E8E16 0E8F16 0E9016 0E9116 0E9216 0E9316 0E9416 0E9516 0E9616 0E9716 0E9816 0E9916 0E9A16 0E9B16 0E9C16 0E9D16 0E9E16 0E9F16 0EA016 0EA116 0EA216 0EA316 0EA416 0EA516 0EA616 0EA716 0EA816 0EA916 0EAA16 0EAB16 0EAC16 0EAD16 0EAE16 0EAF16 0EB016 0EB116 0EB216 0EB316 0EB416 0EB516 0EB616 0EB716 0EB816 0EB916 0EBA16 0EBB16 0EBC16 0EBD16 0EBE16 0EBF16 0EC016 0EC116 0EC216 0EC316 0EC416 0EC516 0EC616 0EC716 0EC816 0EC916 0ECA16 0ECB16 0ECC16 0ECD16 0ECE16 0ECF16 0ED016 0ED116 0ED216 0ED316 0ED416 0ED516 0ED616 0ED716 0ED816 0ED916 0EDA16 0EDB16 0EDC16 0EDD16 0EDE16 0EDF16
Timing for start (The first data of FLDP3)
The last timing (The last data of FLDP1)
FLDP1 data area
Timing for start (The first data of FLDP1)
The last timing (The last data of FLDP0)
FLDP0 data area
Timing for start (The first data of FLDP0)
The last timing (The last data of FLDP2)
FLDP2 data area
Timing for start (The first data of FLDP2)
0E0016 0E0116 0E0216 0E0316 0E0416 0E0516 0E0616 0E0716 0E0816 0E0916 0E0A16 0E0B16 0E0C16 0E0D16 0E0E16 0E0F16 0E1016 0E1116 0E1216 0E1316 0E1416 0E1516 0E1616 0E1716 0E1816 0E1916 0E1A16 0E1B16 0E1C16 0E1D16 0E1E16 0E1F16 0E2016 0E2116 0E2216 0E2316 0E2416 0E2516 0E2616 0E2716 0E2816 0E2916 0E2A16 0E2B16 0E2C16 0E2D16 0E2E16 0E2F16 0E3016 0E3116 0E3216 0E3316 0E3416 0E3516 0E3616 0E3716 0E3816 0E3916 0E3A16 0E3B16 0E3C16 0E3D16 0E3E16 0E3F16 0E4016 0E4116 0E4216 0E4316 0E4416 0E4516 0E4616 0E4716 0E4816 0E4916 0E4A16 0E4B16 0E4C16 0E4D16 0E4E16 0E4F16 0E5016 0E5116 0E5216 0E5316 0E5416 0E5516 0E5616 0E5716 0E5816 0E5916 0E5A16 0E5B16 0E5C16 0E5D16 0E5E16 0E5F16 0E6016 0E6116 0E6216 0E6316 0E6416 0E6516 0E6616 0E6716 0E6816 0E6916 0E6A16 0E6B16 0E6C16 0E6D16 0E6E16 0E6F16
The last timing (The last data of FLDP6)
FLDP6 data area Timing for start (The first data of FLDP6)
The last timing (The last data of FLDP5)
FLDP5 data area
Timing for start (The first data of FLDP5)
The last timing (The last data of FLDP4)
FLDP4 data area
Timing for start (The first data of FLDP4)
The last timing (The last data of FLDP3)
FLDP3 data area
Fig. 53 Example of using FLD automatic display RAM in 32-timing mode
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HARDWARE
FUNCTIONAL DESCRIPTION
Timing Setting
Each timing is set by the FLDC mode register, Tdisp time set register, Toff1 time set register, and Toff2 time set register.
(3) Toff2 time setting
The Toff2 time is time for dark display. For bright display, the FLD display output remains effective until the counter that is counting Tdisp underflows. For dark display, however, "L" (or "off") signal is output when the counter that is counting Toff2 underflows. This Toff2 time setting is valid only for FLD ports which are in the gradation display mode and whose gradation display control RAM value is "1" . Set the Toff2 time by the Toff2 time set register. Make sure the value set to Toff2 is smaller than Tdisp but larger than Toff1. Supposing that the value of the Toff2 time set register is n2, the Toff2 time is represented as Toff2 = n2 t. When the Tdisp counter count source selection bit of the FLDC mode register is "0" and the value of the Toff2 time set register is 180 (B416), Toff2 = 180 4.0 s (at XIN = 4 MHz) = 720 s. When bit 7 of the FLD output control register (address 0EFC16) is set to "1", be sure to set the value of 0316 or more to the Toff2 time set register (address 0EF716).
(1) Tdisp time setting
The Tdisp time means the length of display timing. In non-gradation display mode, it consists of the FLD display output term and the Toff1 time. In gradation display mode, it consists of the display output term and the Toff1 time plus a low signal output term for dark display. Set the Tdisp time by the Tdisp counter count source selection bit of the FLDC mode register and the Tdisp time set register. Supposing that the value of the Tdisp time set register is n, the Tdisp time is represented as Tdisp = (n+1) t (t: count source). When the Tdisp counter count source selection bit of the FLDC mode register is "0" and the value of the Tdisp time set register is 200 (C816), the Tdisp time is: Tdisp = (200 + 1) 4.0 s (at XIN = 4 MHz) = 804 s. When reading the Tdisp time set register, the counting value is read out.
(2) Toff1 time setting
The Toff1 time means a non-output (low signal output) time to prevent blurring of FLD and for dimmer display. Use the Toff1 time set register to set this Toff1 time. Make sure the value set to Toff1 is smaller than Tdisp and Toff2. Supposing that the value of the Toff1 time set register is n1, the Toff1 time is represented as Toff1 = n1 t. When the Tdisp counter count source selection bit of the FLDC mode register is "0" and the value of the Toff1 time set register is 30 (1E16), Toff1 = 30 4.0 s (at XIN = 4 MHz) = 120 s. Be sure to set the value of 0316 or more to the Toff1 time set register (address 0EF616).
Low output term for blurring prevention
Display output term
*Gradation display mode is not selected (Address 0EF416 bit 5 = "0") *Gradation display mode is selected and set for bright display (Address 0EF416 bit 5 = "1" and the corresponding gradation display control data = "0")
Toff1 Tdisp
Low output term for blurring prevention Display output term
Low output term for dark display
*Gradation display mode is selected and set for dark display (Address 0EF416 bit 5 = "1" and the corresponding gradation display control data = "1")
Toff1 Toff2 Tdisp
Fig. 54 FLD and digit output timing
38B7 Group User's Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
FLD Automatic Display Start
Automatic display starts by setting both the automatic display control bit (bit 0 of address 0EF416) and the display start bit (bit 1 of address 0EF416) to "1". The RAM contents at a location apart from the start address of the automatic display RAM for each port by (FLD data pointer (address 0EF816) - 1) are output to each port. The FLD data pointer (address 0EF816) counts down in the Tdisp interval. When the count results in "FF16", the pointer is reloaded and starts counting over again. Before setting the display start bit (bit 1 of address 0EF416) to "1", be sure to set the FLD/port switch registers, digit output set switch registers, FLDC mode register, Tdisp time set register, Toff1 time set register, Toff2 time set register, and FLD data pointer. During FLD automatic display, the display star t bit always keeps "1", and FLD automatic display can be interrupted by writing "0" to this bit.
Key-scan and Interrupt
Either the FLD digit interrupt or FLD blanking interrupt can be selected using the Tscan control bits (bits 2, 3 of address 0EF416). The FLD digit interrupt is generated when the Toff1 time in each timing expires (at rising edge of digit output). Key scanning that makes use of FLD digits can be achieved using each FLD digit interrupt. To use FLD digit interrupts for key scanning, follow the procedure described below: (1) Read the port value each time the interrupt occurs. (2) The key is fixed on the last digit interrupt. The output digit positions can be determined by reading the FLD data pointer (address 0EF816).
Repeat cycle Tdisp
Toff1
Tn FLD digit output
Tn-1 Tn-2
T4
T3
T2
T1
Tn
Tn-1 Tn-2
T4
FLD digit interrupt generated at the rising edge of digit (each timing)
Fig. 55 Timing using digit interrupt
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HARDWARE
FUNCTIONAL DESCRIPTION
The FLD blanking interrupt is generated when the FLD data pointer (address 0EF816) reaches "FF16". The FLD automatic display output is turned off for a duration of 1 Tdisp, 2 Tdisp, or 3 Tdisp depending on post-interrupt settings. During this time, key scanning that makes use of FLD segments can be achieved. When the key scanning is performed with the segment during key-scan blanking time Tscan, follow the procedure described below: (1) Write "0" to the automatic display control bit (bit 0 of address 0EF416). (2) Set the port corresponding to the segment for key scanning to the output port. (3) Perform key scanning. (4) Write "1" to the automatic display control bit.
s Note
When performing a key-scan according to the above steps 1 to 4, take the following points into consideration. 1. Do not set the display start bit (bit 1 of address 0EF416) to "0". 2. Do not set "1" in the ports corresponding to digits.
Repeat cycle Tdisp Tn FLD digit output Segment setting by software FLD blanking interrupt generated at the falling of edge of the last timing Tn-1 Tn-2 T4 T3 T2 T1 Tscan Tn Tn-1 Tn-2
Fig. 56 Timing using FLD blanking interrupt
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HARDWARE
FUNCTIONAL DESCRIPTION
P64 to P67 Expansion Function
Ports P64 to P67 are CMOS output structure. FLD digit outputs can be increased as many as 16 lines by connecting a decoder converting 4-bit to 16-bit data to these ports. P64 to P67 have the function to allow for connection to a decoder converting 4-bit to 16-bit data.
(3) P64 to P67 FLD output reverse function
P64 to P67 have the function to reverse the polarity of the FLD output. This function is useful in adjusting the polarity when using an externally installed driver. The output polarity can be reversed by setting the P64 to P67 output reverse bit of the FLD output control register (bit 0 of address 0EFC16) to "1".
(1) P64 to P67 Toff invalid function
This function disables the Toff1 time and Toff2 time and outputs display data for the duration of Tdisp. (See Figure 57.) This can be achieved by setting the P64 to P67 Toff invalid bit (bit 2 of address 0EFC16) to "1".
s Note
In the case of gradation display mode and dark display, P64 to P67 Toff invalid function is disabled.
(2) Dimmer signal output function
This function allows a dimmer signal creation signal to be output from DIMOUT (P73). The dimmer function can be achieved by controlling the decoder with this signal. (See Figure 57.) This function can be set by setting P73 dimmer output control bit (bit 4 of address 0EFC16) to "1". Unlike the Toff section generating/nothing function, this function disables all display data.
*Gradation display mode is not selected *Gradation display mode is selected and set for bright display (gradation display control data = "0")
FLD output
*Gradation display mode is selected and set for dark display (gradation display control data = "1")
*Gradation display mode is selected and Toff2 SET/RESET switch bit is "1" (gradation display control data = "1")
Toff1 Toff2 Tdisp
Output selecting P64 to P67 Toff invalid
For dimmer signal DIMOUT (P73)
Fig. 57 P64 to P67 FLD output pulses
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HARDWARE
FUNCTIONAL DESCRIPTION
Toff Section Generate/Nothing Function
The function is for reduction of useless noises which generated as every switching of ports, because of the combined capacity of among FLD ports. When the continuous data is output to each FLD port, the Toff1 section of the continuous par ts is not generated. (See Figure 58) If it needs Toff1 section on FLD pulses, set the generating /not of CMOS port Toff section selection bit (bit 5 of address 0EFC16) to "1" and set the generating /not of high-breakdown-voltage port Toff section selection bit to "1". High-breakdown-voltage ports (P2, P0, P1, P3, P4, P5, P63 to P60, total 52 pins) generate Toff1 section by setting the generating /not of high-breakdown-voltage port Toff section selection bit to "1". The CMOS ports (P64 to P67, total 4 pins ) generate Toff1 section by setting the generating /not of CMOS port Toff section selection bit to "1".
Tdisp Toff1 "H" output P1X Output waveform when generating/not of high-breakdown voltage port Toff section selection P2X bit (bit 6 of address 0EFC16) is "1". "H" output "H" output "L" output "H" output "L" output "H" output "H" output
"H" output P1X Output waveform when generating/not of high-breakdown voltage port Toff section selection bit (bit 6 of address 0EFC16) is "0". P2X
"L" output
"H" output
"H" output
Section of Toff1 is not generated because of output is the same. "H" output "H" output "L" output "H" output
Section of Toff1 is not generated because of output is the same.
Fig. 58 Toff section generating/nothing function
Toff2 SET/RESET Switch Function
In gradation display mode, the values set by the Toff2 time set register (TOFF2) are effective. When the Toff2 SET/RESET switch bit of FLD output control register (bit 7 of address 0EFC16) is "0", RAM data is output to the FLD output ports (SET) at the time that is set by TOFF1 and it is turned to "0" (RESET) at the time that is set by TOFF2. When Toff2 SET/RESET switch bit is "1", RAM data is output (SET) at the time that is set by TOFF2 and it is turned to "0" (RESET) when the Tdisp time expires.
s Note
In the case of gradation display mode and dark display, the Toff section generate/nothing function is disabled.
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HARDWARE
FUNCTIONAL DESCRIPTION
Digit Pulses Output Function
P00 to P07 and P20 to P27 can output digit pulses by using the digit output set switch registers. Set the digit output set switch registers by setting as many consecutive 1s as the timing count from P20. The contents of FLD automatic display RAM for the ports that have been selected for digit output are disabled, and the pulse shown in Figure 59 is output automatically. The output timing consists of Tdisp time and Toff1 time, and Toff2 time does not exist. Because the contents of FLD automatic display RAM are disabled, the segment data can be changed easily even when segment data and digit data coexist at the same address in the FLD automatic display RAM. This function is effective in 16-timing*ordinary mode and 16-timing gradation display mode. If a value is set exceeding the timing count (FLD data pointer reload register's set value + 1) for any port, the output of such port is "L".
Tdisp Toff1
P07 P06 P05 P04 P03 P02 P01 P00 P27 P26 P25 P24 P23 P22 P21 P20
Low-order 4bits of the data pointer
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Fig. 59 Digit pulses output function
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HARDWARE
FUNCTIONAL DESCRIPTION
A-D CONVERTER
The 38B7 group has a 10-bit A-D converter. The A-D converter performs successive approximation conversion. Note that the comparator is constructed linked to a capacitor, so that set f(XIN) to at least 250 kHz during A-D conversion. Additionally, bit 7 of the CPU mode register (address 003B16) must be set to "0".
[A-D Conversion Register] ADH, ADL
One of these registers is a high-order register, and the other is a low-order register. The high-order 8 bits of a conversion result is stored in the A-D conversion register (high-order) (address 003416), and the low-order 2 bits of the same result are stored in bit 7 and bit 6 of the A-D conversion register (low-order) (address 003316). During A-D conversion, do not read these registers.
b7 b6 b5 b4 b3 b2 b1 b0
AD/DA control register (ADCON: address 003216) Analoginput pin selection bits
b3b2b1b0
[AD/DA Control Register] ADCON
This register controls A-D converter. Bits 3 to 0 are analog input pin selection bits. Bit 4 is an AD conversion completion bit and "0" during A-D conversion. This bit is set to "1" upon completion of AD conversion. A-D conversion is started by writing "0" in this bit.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVss and VREF by 1024, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports PA7/AN7-PA0/ AN0, and P97/BUZ02/AN15 to P90/SIN3/AN8 and inputs it to the comparator.
0 0 0 0 : PA0/AN0 0 0 0 1 : PA1/AN1 0 0 1 0 : PA2/AN2 0 0 1 1 : PA3/AN3 0 1 0 0 : PA4/AN4 0 1 0 1 : PA5/AN5 0 1 1 0 : PA6/AN6 0 1 1 1 : PA7/AN7 1 0 0 0 : P90/SIN3/AN8 1 0 0 1 : P91/SOUT3/AN9 1 0 1 0 : P92/SCLK3/AN10 1 0 1 1 : P93/SRDY3/AN11 1 1 0 0 : P94/RTP1/AN12 1 1 0 1 : P95/RTP0/AN13 1 1 1 0 : P96/PWM0/AN14 1 1 1 1 : P97/BUZ02/AN15 AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Not used (returns "0" when read) DA output enable bit 0 : DA output disabled 1 : DA output enabled Not used (returns "0" when read) AD conversion register (high-order) (ADH: address 003416) AD conversion register (low-order) (ADL: address 003316)
b7 b0
[Comparator and Control Circuit]
The comparator and control circuit compares an analog inputvoltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to "1".
b9 b8 b7 b6 b5 b4 b3 b2 b7 b1 b0 b0
Note: When reading the low-order 6 bits at address 003316, "0" is read out.
Fig. 60 Structure of AD/DA control register
Data bus
b7 b0
AD/DA control register
4
PA0/AN0 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 P90/SIN3/AN8 P91/SOUT3/AN9 P92/SCLK3/AN10 P93/SRDY3/AN11 P94/RTP1/AN12 P95/RTP0/AN13 P96/PWM0/AN14 P97/BUZ02/AN15
Fig. 61 Block diagram of A-D converter
A-D control circuit
A-D interrupt request
Comparator
A-D conversion register (H) A-D conversion register (L)
Channel selector
(Address 003416)
(Address 003316)
Resistor ladder
AVSS VREF
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HARDWARE
FUNCTIONAL DESCRIPTION
D-A CONVERTER
The 38B7 group has one internal D-A converter with 8-bit resolution. The D-A conversion is performed by setting the value in the D-A conversion register. The result of D-A conversion is output from the DA pin by setting the DA output enable bit to "1". When using the D-A converter, the PB0/DA port direction register bit must be set to "0" (input status). The output analog voltage V is determined by the value n (decimal notation) in the D-A conversion register as follows: V = VREF n/256 (n = 0 to 255) Where VREF is the reference voltage. At reset, the D-A conversion register is cleared to "0016", and the DA output enable bit is cleared to "0", and PB0/DA pin becomes high impedance. The DA output does not have buffers. Accordingly, connect an external buffer when driving a low-impedance load. Set VCC to 3.0 V or more when using the D-A converter. Fig. 62 Block diagram of D-A converter
Data bus
D-A conversion register (8) DA output enable bit PB0/DA
R-2R resistor ladder
"0" DA output enable bit R PB0/DA "1" MSB D-A conversion register "0" "1" 2R
R
R
R
R
R
R
2R
2R
2R
2R
2R
2R
2R
2R LSB
AVSS VREF
Fig. 63 Equivalent connection circuit of D-A converter
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HARDWARE
FUNCTIONAL DESCRIPTION
PWM (Pulse Width Modulation)
The 38B7 group has a PWM function with a 14-bit resolution. When the oscillation frequency XIN is 4 MHz, the minimum resolution bit width is 250 ns and the cycle period is 4096 s. The PWM timing generator supplies a PWM control signal based on a signal that is the frequency of the XIN clock. The explanation in the rest assumes XIN = 4 MHz.
Data bus
It is set to "1" when write.
PWM register (low-order) (address 003616)
bit7 bit5 bit0
bit7
bit0
PWM register (high-order) (address 003516) PWM latch (14-bit)
MSB LSB
14
P96 latch P96/PWM0 PWM P96/PWM output selection bit P96/PWM output selection bit P96 direction register
14-bit PWM circuit
When the internal XCIN 1/2 system clock selection bit is set (64 s cycle) Timing "1" to "0" generating XIN unit for PWM (4096 s cycle) (4MHz) "0"
Fig. 64 PWM block diagram
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HARDWARE
FUNCTIONAL DESCRIPTION
Data Setup
The PWM output pin also function as port P96. Set port P96 to be the PWM output pin by setting bit 0 of the PWM control register (address 002616) to "1". The high-order 8 bits of output data are set in the high-order PWM register PWMH (address 003516) and the low-order 6 bits are set in the low-order PWM register PWML (address 003616).
Transfer From Register to Latch
Data written to the PWML register is transferred to the PWM latch once in each PWM period (every 4096 s), and data written to the PWMH register is transferred to the PWM latch once in each subperiod (every 64 s). Pulses output from the PWM output pin correspond to this latch contents. When the PWML register is read, the contents of the latch are read. However, bit 7 of the PWML register indicates whether the transfer to the PWM latch is completed: the transfer is completed when bit 7 is "0", it is not done when bit 7 is "1". Table 11 Relationship between low-order 6-bit data and setting period of ADD bit Low-order Sub-periods tm lengthened (m = 0 to 63) 6-bit data
LSB
PWM Operation
The timing of the 14-bit PWM function is shown in Figure 65. The 14-bit PWM data is divided into the low-order 6 bits and the high-order 8 bits in the PWM latch. The high-order 8 bits of data determine how long an "H" level signal is output during each sub-period. There are 64 sub-periods in each period, and each sub-period t is 256 (= 64 s) long. The signal's "H" has a length equal to N times , and its minimum resolution = 250 ns. The last bit of the sub-period becomes the ADD bit which is specified either "H" or "L," by the contents of PWML. As shown in Table 11, the ADD bit is decided either "H" or "L." That is, only in the sub-period tm shown in Table 11 in the PWM cycle period T = 64 t, the "H" duration is lengthened during the minimum resolution width period in comparison with the other period. For example, if the high-order eight bits of the 14-bit data are "0316" and the low-order six bits are "0516," the length of the "H" level output in sub-periods t8, t24, t32, t40 and t56 is 4 , and its length 3 in all other sub-periods. Time at the "H" level of each sub-period almost becomes equal because the time becomes length set in the high-order 8 bits or becomes the value plus t, and this sub-period t (= 64 s, approximate 15.6 kHz) becomes cycle period approximately.
000000 000001 000010 000100 001000 010000 100000
None m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63
4096 s 64 s m=0 64 s m=7 64 s m=8 64 s m=9 64 s m = 63
15.75 s
15.75 s
15.75 s
16.0 s
15.75 s
15.75 s
15.75 s
Pulse width modulation register H: 00111111 Pulse width modulation register L: 000101 Sub-periods where "H" pulse width is 16.0 s: m = 8, 24, 32, 40, 56 Sub-periods where "H" pulse width is 15.75 s: m = all other values
Fig. 65 PWM timing
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FUNCTIONAL DESCRIPTION
b7 b0 PWM control register (PWMCON: address 002616) P96/PWM0 output selection bit 0: I/O port 1: PWM0 output Not used (return "0" when read)
Fig. 66 Structure of PWM control register
Data 6A16 stored at address 003516 PWM register (high-order) 5916 6A16 Bit 7 cleared after transfer 2416 Transfer from register to latch PWM latch (14-bit) 165316 1A9316 1AA416 T = 4096 s (64 64 s) t = 64 s 1AA416 B516 1EE416 Data 7B16 stored at address 003516 7B16 Data 3516 stored at address 003616 3516 Transfer from register to latch 1EF516
Data 2416 stored at address 003616 PWM register (low-order) 1316 A416
When bit 7 of PWML is "0," transfer from register to latch is disabled.
(Example 1) PWM output 1 Low-order 6-bits output H = 6A16 L = 2416
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6B
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
5
5
5
5
5
2
5
5
5 106 64
5 36
5
5
5
5
5
6B16............36 times (107)
6A16............28 times (106)
(Example 2) PWM output
6A
6A
6A
6A
6B
6A
6B
6A
6B
6A
6A
6A
6B
6A
6B
6A
6B
6A
6A
6A
6B
6A
6B
6A
6B
6A
6A
Low-order 6 bits output H = 6A16 L = 1816
4
3
4
4 6A16............40 times
3
4 106 64 24
4
3
4
6B16............24 times
t = 64 s (256 0.25 s) Minimum bit width
= 0.25 s
6A 69 68 67 ......... 02 01 ADD FF FE FD FC ......... 97 96 95 ......... 02 01 00 FF FE FD FC ......... 97 96 95 ......... 6A 69 68 67 ......... 02 01
PWM output 2
6B ADD
8-bit counter
02
01
00
The ADD portions with additional are determined either "H" or "L" by low-order 6-bit data.
"H" period length specified by PWMH
256
(64 s), fixed
Fig. 67 14-bit PWM timing
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HARDWARE
FUNCTIONAL DESCRIPTION
INTERRUPT INTERVAL DETERMINATION FUNCTION
The 38B7 group has an interrupt interval determination circuit. This interrupt interval determination circuit has an 8-bit binary up counter. Using this counter, it determines a duration of time from the rising edge (falling edge) of an input signal pulse on the P72/ INT2 pin to the rising edge (falling edge) of the signal pulse that is input next. How to determine the interrupt interval is described below. 1. Enable the INT2 interrupt by setting bit 2 of the interrupt control register 1 (address 003E16). Select the rising interval or falling interval by setting bit 2 of the interrupt edge selection register (address 003A16). 2. Set bit 0 of the interrupt interval determination control register (address 003116) to "1" (interrupt interval determination operating). 3. Select the sampling clock of 8-bit binary up counter by setting bit 1 of the interrupt interval determination control register. 4. When the signal of polarity which is set on the INT2 pin (rising or falling edge) is input, the 8-bit binary up counter starts counting up of the selected counter sampling clock. 5. When the signal of polarity selected above is input again, the value of the 8-bit binary up counter is transferred to the interrupt interval determination register (address 003016), and the remote control interrupt request occurs. Immediately after that, the 8-bit binary up counter continues to count up again from "0016". 6. When count value reaches "FF16", the 8-bit binary up counter stops counting up. Then, simultaneously when the next counter sampling clock is input, the counter sets value "FF16" to the interrupt interval determination register to generate the counter overflow interrupt request.
Noise Filter
The P72/INT2 pin builds in the noise filter. The noise filter operation is described below. 1. Select the sampling clock of the input signal with bits 2 and 3 of the interrupt interval determination control register. When not using the noise filter, set "0016". 2. The P72/INT2 input signal is sampled in synchronization with the selected clock. When sampling the same level signal in a series of three sampling, the signal is recognized as the interrupt signal, and the interrupt request occurs. When setting bit 4 of interrupt interval determination control register to "1", the interrupt request can occur at both rising and falling edges. When using the noise filter, set the minimum pulse width of the INT2 input signal to 3 cycles or more of the sample clock.
Internal system clock selection bit f(XIN)/128 f(XCIN)
Counter sampling clock selection bit 1/1
Divider
1/2
8-bit binary up counter
Counter overflow interrupt request or remote control interrupt request
INT2 interrupt input
Noise filter
Interrupt interval determination register
address 003016
Noise filter sampling clock selection bit 1/1
One-sided/both-sided edge detection selection bit 1/4 1/2
Data bus
Divider
f(XIN)/32 f(XCIN) Internal system clock selection bit
Fig. 68 Interrupt interval determination circuit block diagram
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FUNCTIONAL DESCRIPTION
b7 b0
Interrupt interval determination control register (IIDCON: address 003116) Interrupt interval determination circuit operating selection bit 0 : Stopped 1 : Operating Counter sampling clock selection bit 0 : f(XIN)/128 or f(XCIN) 1 : f(XIN)/256 or f(XCIN)/2 Noise filter sampling clock selection bits (INT2)
b3b2
0 0 : Filter stop 0 1 : f(XIN)/32 or f(XCIN) 1 0 : f(XIN)/64 or f(XCIN)/2 1 1 : f(XIN)/128 or f(XCIN)/4 One-sided/both-sided edge detection selection bit 0 : One-sided edge detection 1 : Both-sided edge detection (can be used when using a noise filter) Not used (return "0" when read) (Do not write "1" to these bits.)
Fig. 69 Structure of interrupt interval determination control register
(When IIDCON4 = "0") Noise filter sampling clock INT2 pin
Acceptance of interrupt
Counter sampling clock N 8-bit binary up counter value N Interrupt interval determination register value N Remote control interrupt request Remote control interrupt request 0 1 2 3 4 6 0 6 6 Counter overflow interrupt request 1 2 3 FE FF 0 FF FF 1
5
~ ~
Fig. 70 Interrupt interval determination operation example (at rising edge active)
(When IIDCON4 = "1") Noise filter sampling clock INT2 pin
Acceptance of interrupt
Counter sampling clock N 8-bit binary up counter value N Interrupt interval determination register value N Remote control interrupt request Remote control interrupt request 0 1 2 0 2 2 1 2 3 0 3 3 Remote control interrupt request Remote control interrupt request 1 2 0 2 2 1 2 FE FF 0 FF FF Counter overflow interrupt request 1
Fig. 71 Interrupt interval determination operation example (at both-sided edge active)
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HARDWARE
FUNCTIONAL DESCRIPTION
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software runaway). The watchdog timer consists of an 8-bit watchdog timer L and a 8-bit watchdog timer H.
(2) Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 0EEE16) permits selecting a watchdog timer H count source. When this bit is set to "0", the underflow signal of watchdog timer L becomes the count source. The detection time is set to 131.072 ms at f(XIN) = 4 MHz frequency, and 32.768 s at f(XCIN) = 32 kHz frequency. When this bit is set to "1", the count source becomes the signal divided by 8 for f(XIN) or divided by 16 for f(XCIN). The detection time in this case is set to 512 s at f(XIN) = 4 MHz frequency, and 128 ms at f(XCIN) = 32 kHz frequency. This bit is cleared to "0" after reset.
Standard Operation Of Watchdog Timer
When any data is not written into the watchdog timer control register (address 0EEE16) after reset, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register and an internal reset occurs at an underflow of the watchdog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register may be started before an underflow. When the watchdog timer control register is read, the values of the high-order 6 bits of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read.
(3) Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 0EEE16) permits disabling the STP instruction when the watchdog timer is in operation. When this bit is "0", the STP instruction is enabled. When this bit is "1", the STP instruction is disabled. If the STP instruction is executed, an internal resetting occurs. When this bit is set to "1", it cannot be rewritten to "0" by program. This bit is cleared to "0" after reset.
(1) Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address 0EEE16), a watchdog timer H is set to "FF16" and a watchdog timer L to "FF16".
s Note
When releasing the stop mode, the watchdog timer performs its count operation even in the stop release waiting time. Be careful not to cause the watchdog timer H to underflow in the stop release waiting time, for example, by writing any data in the watchdog timer control register (address 0EEE16) before executing the STP instruction.
XCIN
1/2 "1" Internal system clock selection bit (Note) "0"
"FF16" is set when watchdog timer control register is written to. Watchdog timer L (8) 1/8
Data bus "FF16" is set when watchdog timer control register is written to.
"0" "1" Watchdog timer H (8)
XIN
Watchdog timer H count source selection bit
STP instruction disable bit STP instruction Reset circuit Internal reset
RESET
Note: Either high-speed, middle-speed or low-speed mode is selected by bit 7 of CPU mode register.
Fig. 72 Block diagram of watchdog timer
b7
b0
Watchdog timer control register (WDTCON : address 0EEE16)
Watchdog timer H (for read-out of high-order 6 bits) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/8 or f(XCIN)/16
Fig. 73 Structure of watchdog timer control register
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FUNCTIONAL DESCRIPTION
BUZZER OUTPUT CIRCUIT
The 38B7 group has a buzzer output circuit. One of 1 kHz, 2 kHz and 4 kHz (at XIN = 4.19 MHz) frequencies can be selected by the buzzer output control register (address 0EFD16). Either P77/BUZ01 or P97/BUZ02/AN15 can be selected as a buzzer output port by the output port selection bits (b2 and b3 of address 0EFD16). The buzzer output is controlled by the buzzer output ON/OFF bit (b4). Note: In the low-speed mode, a buzzer output is made OFF.
Port latch f(XIN)
1/1024 1/2048 1/4096
Divider
Buzzer output
Buzzer output ON/OFF bit Output port control signal Port direction register
Fig. 74 Block diagram of buzzer output circuit
b7
b0
Buzzer output control register (BUZCON: address 0EFD16) Output frequency selection bits (XIN = 4.19 MHz)
b1b0
0 0 : 1 kHz (f(XIN)/4096) 0 1 : 2 kHz (f(XIN)/2048) 1 0 : 4 kHz (f(XIN)/1024) 1 1 : Not available Output port selection bits
b3b2
0 0 : P77 and P97 function as ordinary ports. 0 1 : P77/BUZ01 functions as a buzzer output. 1 0 : P97/BUZ02/AN15 functions as a buzzer output. 1 1 : Not available Buzzer output ON/OFF bit
b4
0 : Buzzer output OFF ("0" output) 1 : Buzzer output ON Not used (returns "0" when read)
Fig. 75 Structure of buzzer output control register
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HARDWARE
FUNCTIONAL DESCRIPTION
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an "L" level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between 2.7 V and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (loworder byte). Make sure that the reset input voltage is less than 0.54 V for Vcc of 2.7 V (switching to the high-speed mode, a power source voltage must be between 4.0 V and 5.5 V).
Poweron Power source voltage 0V Reset input voltage 0V (Note)
RESET
VCC
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
VCC Power source voltage detection circuit
Fig. 76 Reset circuit example
XIN
RESET Internal reset
Address
?
?
?
?
FFFC
FFFD
ADH, ADL
Data
ADL
ADH
SYNC
XIN: about 4000 cycles Notes 1: The frequency relation of f(XIN) and f() is f(XIN)=4 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 77 Reset sequence
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FUNCTIONAL DESCRIPTION
Address Register contents (1) Port P0 (2) Port P1 (3) Port P1 direction register (4) Port P2 (5) Port P3 (6) Port P3 direction register (7) Port P4 (8) Port P4 direction register (9) Port P5 (10) Port P5 direction register (11) Port P6 (12) Port P6 direction register (13) Port P7 (14) Port P7 direction register (15) Port P8 (16) Port P8 direction register (17) Port P9 (18) Port P9 direction register (19) Port PA (20) Port PA direction register (21) Port PB (22) Port PB direction register (23) Serial I/O1 control register 1 (24) Serial I/O1 control register 2 (25) Serial I/O1 control register 3 (26) Serial I/O2 control register (27) Serial I/O2 status register (28) Timer 1 (29) Timer 2 (30) Timer 3 (31) Timer 4 (32) Timer 5 (33) Timer 6 (34) PWM control register (35) Timer 12 mode register (36) Timer 34 mode register (37) Timer 56 mode register 000016 000216 000316 000416 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001916 001A16 001C16 001D16 001E16 002016 002116 002216 002316 002416 002516 002616 002816 002916 002A16 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 8016 FF16 0116 FF16 FF16 FF16 FF16 0016 0016 0016 0016 (38) D-A conversion register (39) Timer X (low-order) (40) Timer X (high-order) (41) Timer X mode register 1 (42) Timer X mode register 2 (43) Interrupt interval determination register (44) Interrupt interval determination control register (45) AD/DA control register (46) UART control register (47) Interrupt source switch register (48) Interrupt edge selection register (49) CPU mode register (50) Interrupt request register 1 (51) Interrupt request register 2 (52) Interrupt control register 1 (53) Interrupt control register 2 (54) Serial I/O3 control register (55) Watchdog timer control register (56) Pull-up control register 3 (57) Pull-up control register 1 (58) Pull-up control register 2 (59) Port P0 digit output set switch register (60) Port P2 digit output set switch register (61) FLDC mode register (62) Tdisp time set register (63) Toff1 time set register (64) Toff2 time set register Address Register contents 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003816 003916 003A16 0016 FF16 FF16 0016 0016 0016 0016 1016 8016 0016 0016
003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 0EEC16 0EEE16 0EEF16 0EF016 0EF116 0EF216 0EF316 0EF416 0EF516 0EF616 0EF716 0016 0016 0016 0016 0016 3F16 0016 0016 0016 0016 0016 0016 0016 FF16 FF16 0016 0016 0016 0016 0016 0016 0016
(65) Port P4 FLD/Port switch register 0EF916 (66) Port P5 FLD/Port switch register 0EFA16 (67) Port P6 FLD/Port switch register 0EFB16 (68) FLD output control register (69) Buzzer output control register (70) Flash memory control register (71) Flash command register (72) Processor status register (73) Program counter 0EFC16 0EFD16 0EFE16 0EFF16
(PS) 1 (PCH) (PCL)
FFFD16 contents FFFC16 contents
: Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 78 Internal status at reset
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HARDWARE
FUNCTIONAL DESCRIPTION
CLOCK GENERATING CIRCUIT
The 38B7 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT or XCIN and XCOUT. Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feedback resistor exists on-chip. However, an external feedback resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports.
Oscillation Control
(1) Stop mode If the STP instruction is executed, the internal system clock stops at an "H" level, and XIN and XCIN oscillators stop. Timer 1 is set to "FF16" and timer 2 is set to "0116". Either XIN divided by 8 or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 12 mode register are cleared to "0". Set the interrupt enable bits of the timer 1 and timer 2 to disabled ("0") before executing the STP instruction. Oscillator restarts when an external interrupt is received, but the internal system clock is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. (2) Wait mode If the WIT instruction is executed, the internal system clock stops at an "H" level. The states of XIN and XCIN are the same as the state before executing the WIT instruction. The internal system clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted.
Frequency Control
(1) Middle-speed mode The internal system clock is the frequency of XIN divided by 4. After reset, this mode is selected. (2) High-speed mode The internal system clock is the frequency of XIN. (3) Low-speed mode The internal system clock is the frequency of XCIN divided by 2. s Note If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3 * f(XCIN). (4) Low power consumption mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set the main clock stop bit (bit 5) of the CPU mode register to "1". When the main clock XIN is restarted (by setting the main clock stop bit to "0"), set enough time for oscillation to stabilize.
XCIN Rf
XCOUT Rd CCOUT
XIN
XOUT
CCIN
CIN
COUT
Fig. 79 Ceramic resonator circuit
XCIN
XCOUT open
XIN
XOUT
open External oscillation circuit VCC VSS
External oscillation circuit or external pulse VCC VSS
Fig. 80 External clock input circuit
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FUNCTIONAL DESCRIPTION
XCIN
XCOUT
"1"
"0"
Port XC switch bit (Note 3)
1/2 XIN XOUT
Internal system clock selection bit (Notes 1, 3) Low-speed mode
"1"
Timer 1 count source selection bit (Note 2)
"1"
Timer 2 count source selection bit (Note 2)
"0"
Timer 1 1/4 1/2
"0"
Timer 2
"1"
"0"
High-speed or middle-speed mode Main clock division ratio selection bits (Note 3) Middle-speed mode
"1" "0"
Timing (internal clock)
Main clock stop bit (Note 3)
High-speed or low-speed mode
Q
S R
STP instruction WIT instruction
SQ R
QS R
STP instruction
Reset Interrupt disable flag l Interrupt request
Notes 1: When low-speed mode is selected, set the port Xc switch bit (b4) to "1". 2: Refer to the structure of the timer 12 mode register. 3: Refer to the structure of the CPU mode register.
Fig. 81 Clock generating circuit block diagram
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HARDWARE
FUNCTIONAL DESCRIPTION
Reset
Middle-speed mode ( =1 MHz) CM7=0(4 MHz selected) CM6=1(middle-speed) CM5=0(XIN oscillating) CM4=0(32 kHz stopped)
CM6 "1"
High-speed mode ( =4 MHz)
"0"
CM7=0(4 MHz selected) CM6=0(high-speed) CM5=0(XIN oscillating) CM4=0(32 kHz stopped)
"0"
4 "0" CM 6 0" " M" "1 C " "1
CM4
"1 "
CM
4
"1"
"0 "
CM6
Middle-speed mode ( =1 MHz) CM7=0(4 MHz selected) CM6=1(middle-speed) CM5=0(XIN oscillating) CM4=1(32 kHz oscillating)
High-speed mode ( =4 MHz)
"1"
"0"
CM7=0(4 MHz selected) CM6=0(high-speed) CM5=0(XIN oscillating) CM4=1(32 kHz oscillating)
"0"
CM7
"1"
CM7
CM6 "1" "0"
Low-speed mode ( =16 kHz) CM7=1(32 kHz selected) CM6=0(high-speed) CM5=0(XIN oscillating) CM4=1(32 kHz oscillating)
Low-speed mode ( =16 kHz) CM7=1(32 kHz selected) CM6=1(middle-speed) CM5=0(XIN oscillating) CM4=1(32 kHz oscillating)
"1"
"0"
"1"
6
"1 "
CM4
"0 "
CM
"0"
b7
b4 CPU mode register (CPUM : address 003B16)
CM4 : Port Xc switch bit 0: I/O port function 1: XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0: Oscillating 1: Stopped CM6: Main clock division ratio selection bit 0: f(XIN) (High-speed mode) 1: f(XIN)/4 (Middle-speed mode) CM7: Internal system clock selection bit 0: XIN-XOUT selected (Middle-/High-speed mode) 1: XCIN-XCOUT selected (Low-speed mode)
"0"
CM5
"1"
"0 "
CM6 "1" "0"
Low-power dissipation mode ( =16 kHz) CM7=1(32 kHz selected) CM6=1(middle-speed) CM5=1(XIN stopped) CM4=1(32 kHz oscillating)
Low-power dissipation mode ( =16 kHz) CM7=1(32 kHz selected) CM6=0(high-speed) CM5=1(XIN stopped) CM4=1(32 kHz oscillating)
Notes 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3: Timer operates in the wait mode. 4: When the stop mode is ended, a delay of approximately 1 ms occurs by Timer 1 in middle-/high-speed mode. 5: When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 in low-speed mode. 6: The example assumes that 4 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. indicates the internal system clock.
Fig. 82 State transitions of system clock
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"1"
" "1
CM " "1
6
" "0
"1 "
CM
C
5
6
"1 "
CM5
M
" "0
"0 "
CM
5
"0"
HARDWARE
FUNCTIONAL DESCRIPTION
Power Dissipation Calculating Method
(Fixed number depending on microcomputer's standard) * VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA * Resistor value = 48 k (min.) * Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V 15 mA = 75 mW (Fixed number depending on use condition) * Apply voltage to VEE pin: Vcc - 45 V * Timing number a; digit number b; segment number c * Ratio of Toff time corresponding Tdisp time: 1/16 * Turn ON segment number during repeat cycle: d * All segment number during repeat cycle: e (= a c) * Total number of built-in resistor: for digit, f; for segment, g * Digit pin current value h (mA) * Segment pin current value i (mA) (1) Digit pin power dissipation {h b (1 - Toff / Tdisp) voltage} / a (2) Segment pin power dissipation {i d (1-Toff / Tdisp) voltage} / a (3) Pull-down resistor power dissipation (digit) {power dissipation per 1 digit (b f / b) (1-Toff / Tdisp) } / a (4) Pull-down resistor power dissipation (segment) {power dissipation per 1 segment (d g / c) (1-Toff / Tdisp) } / a (5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190 mW (1) + (2)+ (3) + (4) + (5) = X mW
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Power Dissipation Calculating Example 1
(Fixed number depending on microcomputer's standard) * VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA * Resistor value 43 V / 900 s = 48 k (min.) * Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V 15 mA = 75 mW (Fixed number depending on use condition) * Apply voltage to VEE pin: Vcc - 45 V * Timing number 17; digit number 16; segment number 20 * Ratio of Toff time corresponding Tdisp time: 1/16 * Turn ON segment number during repeat cycle: 31 * All segment number during repeat cycle: 340 (= 17 20) * Total number of built-in resistor: for digit, 16; for segment, 20 * Digit pin current value 18 (mA) * Segment pin current value 3 (mA) (1) Digit pin power dissipation {18 16 (1 - 1 / 16) 2} / 17 = 31.77 mW (2) Segment pin power dissipation {3 31 (1- 1 / 16) 2} / 17 = 10.26 mW (3) Pull-down resistor power dissipation (digit) [{45 - 2} 2/ 48 (16 16 / 16) (1 - 1 / 16)] / 17 = 33.94 mW (4) Pull-down resistor power dissipation (segment) [{45 - 2} 2/ 48 (31 20 / 20) (1 - 1 / 16)] / 17 = 65.86 mW (5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 75 mW (1) + (2)+ (3) + (4) + (5) = 217 mW
DIG0 DIG1 DIG2 DIG3
DIG13 DIG14 DIG15 Timing number 1 2 3 Repeat cycle Tscan 14 15 16 17
Fig. 83 Digit timing waveform (1)
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Power Dissipation Calculating Example 2 (2 or more digits turned ON at the same time)
(Fixed number depending on microcomputer's standard) * VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA * Resistor value 43 V / 900 s = 48 k (min.) * Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V 15 mA = 75 mW (Fixed number depending on use condition) * Apply voltage to VEE pin: Vcc - 45 V * Timing number 11; digit number 12; segment number 24 * Ratio of Toff time corresponding Tdisp time: 1/16 * Turn ON segment number during repeat cycle: 114 * All segment number during repeat cycle: 264 (= 11 24) * Total number of built-in resistor: for digit, 10; for segment, 22 * Digit pin current value 18 (mA) * Segment pin current value 3 (mA) (1) Digit pin power dissipation {18 12 (1 - 1 / 16) 2} / 11 = 36.82 mW (2) Segment pin power dissipation {3 114 (1- 1 / 16) 2} / 11 = 58.30 mW (3) Pull-down resistor power dissipation (digit) [{45 - 2}2/ 48 (12 10 / 12) (1 - 1 / 16)] / 11 = 32.84 mW (4) Pull-down resistor power dissipation (segment) [{45 - 2}2/ 48 (114 22 / 24) (1 - 1 / 16)] / 11 = 343.08 mW (5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 75 mW (1) + (2)+ (3) + (4) + (5) = 547 mW
DIG0 DIG1 DIG2 DIG3 DIG4 DIG5 DIG6 DIG7 DIG8 DIG9 Timing number 1 2 3 4 5 6 7 8 9 10 11
Repeat cycle Tscan
Fig. 84 Digit timing waveform (2)
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FUNCTIONAL DESCRIPTION
FLASH MEMORY MODE
The M38B79FF has the flash memory mode in addition to the normal operation mode (microcomputer mode). The user can use this mode to perform read, program, and erase operations for the internal flash memory. The M38B79FF has three modes the user can choose: the parallel input/output and serial input/output mode, where the flash memory is handled by using the external programmer, and the CPU reprogramming mode, where the flash memory is handled by the central processing unit (CPU). The following explains these modes.
Functional Outline (parallel input/output mode)
In the parallel input/output mode, the M38B79FF allow the user to choose an operation mode between the read-only mode and the read/write mode (software command control mode) depending on the voltage applied to the VPP pin. When VPP = VPPL, the readonly mode is selected, and the user can choose one of three states ___ ___ (e.g., read, output disable, or standby) depending on inputs ___ to the CE, OE, and WE pins. When VPP = VPPH, the read/write mode is selected, and the user can choose one of four states (e.g., read,__ output disable, standby, or write) depending on inputs __ ___ to the CE, OE, and WE pins. Table 13 shows assignment states of control input and each state. q Read __ The microcomputer enters the read state by driving the CE, and __ ___ OE pins low and the WE pin high; and the contents of memory corresponding to the address to be input to address input pins (A0-A16) are output to the data input/output pins (D0-D7). q Output disable The microcomputer___ enters the output disable state by driving the __ __ CE pin low and the WE and OE pins high; and the data input/output pins enter the floating state. q Standby __ The microcomputer enters the standby state by driving the CE pin high. The M38B79FF is placed in a power-down state consuming only a minimal supply current. At this time, the data input/output pins enter the floating state. q Write The microcomputer enters the write state by driving the VPP pin ___ __ high (VPP = __ VPPH) and then the WE pin low when the CE pin is low and the OE pin is high. In this state, software commands can be input from the data input/output pins, and the user can choose program or erase operation depending on the contents of this software command.
(1) Flash memory mode 1 (parallel I/O mode)
The parallel I/O mode can be selected by connecting wires as shown in Figures 85 and supplying power to the VCC and VPP pins. In this mode, the M38B79FF operates as an equivalent of MITSUBISHI's CMOS flash memory M5M28F101. However, because the M38B79FF's internal memory has a capacity of 60 Kbytes, programming is available for addresses 0100016 to 0FFFF16, and make sure that the data in addresses 0000016 to 00FFF16 and addresses 1000016 to 1FFFF16 are FF16. Note also that the M38B79FF does not contain a facility to read out a device identification code by applying a high voltage to address input (A9). Be careful not to erratically set program conditions when using a general-purpose PROM programmer. Table 12 shows the pin assignments when operating in the parallel input/output mode.
Table 12 Pin assignments of M38B79FF when operating in the parallel input/output mode VCC VPP VSS Address input Data I/O __ CE ___ OE ___ WE M38B79FF VCC CNVSS VSS Ports P0, P1, P31 Port P2 P36 P37 P33 M5M28F101 VCC VPP VSS A0-A16 D0-D7 __ CE __ OE ___ WE
Table 13 Assignment states of control input and each state Pin Mode Read-only State Read Output disable Standby Read Output disable Standby Write
__ __ ___
CE VIL VIL VIH VIL VIL VIH VIL
OE VIL VIH x VIL VIH x VIH
WE VIH VIH x VIH VIH x VIL
VPP VPPL VPPL VPPL VPPH VPPH VPPH VPPH
Data I/O Output Floating Floating Output Floating Floating Input
Read/Write
Note: x can be VIL or VIH.
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Table 14 Pin description (flash memory parallel I/O mode) Pin VCC, VSS CNVSS _____ RESET XIN XOUT AVSS VREF P00-P07 P10-P17 P20-P27 P30-P37 Name Power supply VPP input Reset input Clock input Clock output Analog supply input Reference voltage input Address input (A0-A7) Address input (A8-A15) Data I/O (D0-D7) Control signal input Input /Output -- Input Input Input Output -- Input Input Input I/O Input Functions Supply 5 V 10 % to VCC and 0 V to VSS. Connect to 5 V 10 % in read-only mode, connect to 11.7 V to 12.6 V in read/write mode. Connect to VSS. Connect a ceramic resonator between XIN and XOUT. Connect to VSS. Connect to VSS. Port P0 functions as 8-bit address input (A0-A7). Port P1 functions as 8-bit address input (A8-A15). Function as 8-bit data's I/O pins (D0-D7). Connect them to Vss through each resistor of 6.8 k. P37, P36 and P33 function as the OE, CE and WE input pins respectively. P31 functions as the A16 input pin. Connect P30 and P32 to VSS. Input "H" or "L" to P34, P35, or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Connect P64 and P66 to VSS. Input "H" or "L" to P60-P63, P65, P67, or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Keep this open.
P40-P47 P50-P57 P60-P67 P70-P77 P80-P83 P90-P97 PA0-PA7 PB0-PB6 VEE
Input port P4 Input port P5 Input port P6 Input port P7 Input port P8 Input port P9 Input port PA Input port PB Pull-down power supply
Input Input Input Input Input Input Input Input
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FUNCTIONAL DESCRIPTION
A14
A11
A12 A13
A10
A15
A16
WE
A0 A1
CE
6.8 k
*P27/FLD7 *P26/FLD6 *P25/FLD5 D4 *P24/FLD4 D3 *P23/FLD3 D2 *P22/FLD2 D1 *P21/FLD1 D0 *P20/FLD0 VEE PB6/SIN1 PB5/SOUT1 PB4/SCLK11 PB3/SSTB1 PB2/SBUSY1 PB1/SRDY1 PB0/SCLK12/SVIN/DA AVSS VREF PA7/AN7 PA6/AN6
D7 D6 D5
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
*P00/FLD8 *P01/FLD9 *P02/FLD10 *P03/FLD11 *P04/FLD12 *P05/FLD13 *P06/FLD14 *P07/FLD15 *P10/FLD16 *P11/FLD17 *P12/FLD18 *P13/FLD19 *P14/FLD20 *P15/FLD21 *P16/FLD22 *P17/FLD23 *P30/FLD24 *P31/FLD25 *P32/FLD26 *P33/FLD27 *P34/FLD28 *P35/FLD29 *P36/FLD30 *P37/FLD31 *P40/FLD32 *P41/FLD33 *P42/FLD34 *P43/FLD35 *P44/FLD36 *P45/FLD37
OE
A2
A6
A7
A3
A4
A5
A8
A9
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
M38B79FFFP
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
*P46/FLD38 *P47/FLD39 *P50/FLD40 *P51/FLD41 *P52/FLD42 *P53/FLD43 *P54/FLD44 *P55/FLD45 *P56/FLD46 *P57/FLD47 *P60/FLD48 *P61/FLD49 *P62/FLD50 *P63/FLD51 P64/RxD/FLD52 P65/TxD/FLD53 P66/SCLK21/FLD54 P67/SRDY2/SCLK22/FLD55 P70/INT0 P71/INT1
Vss
Vcc
Fig. 85 Pin connection of M38B79FF when operating in parallel input/output mode
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PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 P97/BUZ02/AN15 P96/PWM0/AN14 P95/RTP0/AN13 P94/RTP1/AN12 P93/SRDY3/AN11 P92/SCLK3/AN10 P91/SOUT3/AN9 P90/SIN3/AN8 P83/CNTR0/CNTR2 P82/CNTR1 Vpp CNVSS RESET P81/XCOUT P80/XCIN VSS XIN XOUT VCC P77/INT4/BUZ01 P76/T3OUT P75/T1OUT P74/PWM1 P73/INT3/DIMOUT P72/INT2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
:Connect to the ceramic oscillation circuit.
* : High-breakdown-voltage output port: Totaling 52
Package type: 100P6S-A
indicates the flash memory pin.
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HARDWARE
FUNCTIONAL DESCRIPTION
Read-only Mode
The microcomputer enters the read-only mode by applying VPPL to the VPP pin. In this mode, the user can input the address of a memory location to be read and the control signals at the timing shown in Figure 86, and the M38B79FF will output the contents of the user's specified address from data I/O pin to the external. In this mode, the user cannot perform any operation other than read.
VIH Address VIL tRC VIH CE VIL ta(CE) VIH OE VIL VIH WE VIL VOH Data VOL Floating ta(OE) tOLZ tCLZ ta(AD) Dout tDH Floating tWRR tDF Valid address
Fig. 86 Read timing
Read/Write Mode
The microcomputer enters the read/write mode by applying VPPH to the VPP pin. In this mode, the user must first input a software command to choose the operation (e. g., read, program, or erase) to be performed on the flash memory (this is called the first cycle), and then input the information necessary for execution of the command (e.g, address and data) and control signals (this is called the second cycle). When this is done, the M38B79FF executes the specified operation. Table 15 Software command (parallel input/output mode) Symbol Read Program Program verify Erase Erase verify Reset Device identification First cycle Address input x x x x Verify address x x
Table 15 shows the software commands and the input/output information in the first and the second cycles. The input address is ___ latched internally at the falling edge of the WE input; software commands ___ other input data are latched internally at the rising and edge of the WE input. The following explains each software command. Refer to Figures 87 to 89 for details about the signal input/output timings.
Data input 0016 4016 C016 2016 A016 FF16 9016
Second cycle Address input Data I/O Read address Read data (Output) Program address Program data (Input) x Verify data (Output) x 2016 (Input) x Verify data (Output) x FF16 (Input) ADI DDI (Output)
Note: ADI = Device identification address : manufacturer's code 0000016, device code 0000116 DDI = Device identification data : manufacturer's code 1C16, device code D016 x can be VIL or VIH.
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q Read command The microcomputer enters the read mode by inputting command code "0016" in the first cycle. The command code is latched into ___ the internal command latch at the rising edge of the WE input. When the address of a memory location to be read is input in the second cycle, with control signals input at the timing shown in Figure 87, the M38B79FF outputs the contents of the specified address from the data I/O pins to the external. The read mode is retained until any other command is latched into the command latch. Consequently, once the M38B79FF enters the read mode, the user can read out the successive memory contents simply by changing the input address and executing the second cycle only. Any command other than the read command must be input beginning from its command code over again each time the user execute it. The contents of the command latch immediately after power-on is 0016.
VIH Address VIL tWC VIH CE VIL tCS VIH OE VIL tRRW VIH WE VIL ta(OE) tDS VIH Data VIL tVSC VPPH VPP VPPL 0016 tDH tOLZ tCLZ ta(AD) Dout tDH tWP tWRR tDF tCH ta(CE) tRC Valid address
Fig. 87 Timings during reading
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q Program command The microcomputer enters the program mode by inputting command code "4016" in the first cycle. The command code ___ is latched into the internal command latch at the rising edge of the WE input. When the address which indicates a program location and data is input in the second cycle, the M38B79FF internally latches the ad___ dress at the___ edge of the WE input and the data at the rising falling edge of the WE input. The M38B79FF starts programming at the ___ rising edge of the WE input in the second cycle and finishes progr amming within 10 s as measured by its internal timer. Programming is performed in units of bytes. Note: A programming operation is not completed by executing the program command once. Always be sure to execute a program verify command after executing the program command. When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer to Figure 90 for the programming flowchart. q Program verify command The microcomputer enters the program verify mode by inputting command code "C016" in the first cycle. This command is used to verify the programmed data after executing the program command. The command code is ___ latched into the internal command latch at the rising edge of the WE input. When control signals are input in the second cycle at the timing shown in Figure 88, the M38B79FF outputs the programmed address's contents to the external. Since the address is internally latched when the program command is executed, there is no need to input it in the second cycle.
VIH Address VIL tWC VIH CE VIL tCS tCH VIH OE VIL tRRW tWP VIH WE VIL tDS VIH Data VIL tVSC VPPH VPP VPPL 4016 tDH
Program verify Program address tAS tAH Program
tCS tCH
tCS tCH
tWPH
tWP
tDP
tWP
tWRR
tDS
tDS
DIN tDH
C016 tDH
Dout Verify data output
Fig. 88 Input/output timings during programming (Verify data is output at the same timing as for read.)
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FUNCTIONAL DESCRIPTION
q Erase command The erase command is executed by inputting command code 2016 in the first cycle and command code 2016 again in the second cycle. The command code is latched into the internal command ___ latch at the rising edges of the WE input in the first cycle and in the second cycle, respectively. The erase operation is initiated at ___ the rising edge of the WE input in the second cycle, and the memory contents are collectively erased within 9.5 ms as measured by the internal timer. Note that data 0016 must be written to all memory locations before executing the erase command. Note: An erase operation is not completed by executing the erase command once. Always be sure to execute an erase verify command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 90 for the erase flowchart. q Erase verify command The user must verify the contents of all addresses after completing the erase command. The microcomputer enters the erase verify mode by inputting the verify address and command code A016 in the first cycle. The address is internally latched at the fall___ ing edge of the WE input, and the command code is internally ___ latched at the rising edge of the WE input. When control signals are input in the second cycle at the timing shown in Figure 89, the M38B79FF outputs the contents of the specified address to the external. Note: If any memory location where the contents have not been erased is found in the erase verify operation, execute the operation of "erase erase verify" over again. In this case, however, the user does not need to write data 0016 to memory locations before erasing.
VIH Address VIL tWC VIH CE VIL tCS tCH VIH OE VIL tRRW tWP VIH WE VIL tDS VIH Data VIL tVSC VPPH VPP VPPL tDH tDH 2016 2016 tDS tWPH tWP tDE tCS tCH Erase
Erase verify Verify address tAS tAH
tCS tCH
tWP
tWRR
tDS
A016
Dout Verify data output
tDH
Fig. 89 Input/output timings during erasing (verify data is output at the same timing as for read.)
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FUNCTIONAL DESCRIPTION
q Reset command The reset command provides a means of stopping execution of the erase or program command safely. If the user inputs command code FF16 in the second cycle after inputting the erase or program command in the first cycle and again input command code FF16 in the third cycle, the erase or program command is disabled (i.e., reset), and the M38B79FF is placed in the read mode. If the reset command is executed, the contents of the memory does not change. q Device identification code command By inputting command code 9016 in the first cycle, the user can read out the device identification code. The command code is latched into the internal command latch at the rising edge of the ___ WE input. At this time, the user can read out manufacture's code 1C16 (i.e., MITSUBISHI) by inputting 000016 to the address input pins in the second cycle; the user can read out device code D016 (i. e., 1M-bit flash memory) by inputting 000116. These command and data codes are input/output at the same timing as for read.
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FUNCTIONAL DESCRIPTION
Program START
Erase START
VCC = 5 V, VPP = VPPH
VCC = 5 V, VPP = VPPH
ADRS = first location
YES
ALL BYTES = 0016 ? NO
X=0 WRITE PROGRAM COMMAND WRITE PROGRAM DATA DURATION = 10 s X=X+1 WRITE PROGRAM-VERIFY COMMAND DURATION = 6 s YES X = 25 ? NO FAIL PASS VERIFY BYTE ? PASS NO INC ADRS LAST ADRS ? NO YES WRITE READ COMMAND 0016 FAIL VERIFY BYTE ? FAIL
4016
PROGRAM ALL BYTES = 0016
ADRS = first location DIN X=0 WRITE ERASE COMMAND WRITE ERASE COMMAND DURATION = 9.5 ms X=X+1 WRITE ERASE-VERIFY COMMAND DURATION = 6 s
2016
C016
2016
A016
X = 1000 ?
YES
PASS VERIFY BYTE ? PASS VERIFY BYTE ? FAIL
VPP = VPPL INC ADRS DEVICE PASSED DEVICE FAILED
NO LAST ADRS ? YES WRITE READ COMMAND 0016
VPP = VPPL
DEVICE PASSED
DEVICE FAILED
Fig. 90 Programming/Erasing algorithm flow chart
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FUNCTIONAL DESCRIPTION
Table 16 DC ELECTRICAL CHARACTERISTICS (Ta = 25 C, VCC = 5 V 10 %, unless otherwise noted) Symbol ISB1 ISB2 ICC1 ICC2 ICC3 IPP1 IPP2 IPP3 VIL VIH VOH1 VOH2 VPPL VPPH VCC supply current (at standby) VCC supply current (at read) VCC supply current (at program) VCC supply current (at erase) VPP supply current (at read) VPP supply current (at program) VPP supply current (at erase) "L" input voltage "H" input voltage "H" output voltage VPP supply voltage (read only) VPP supply voltage (read/write) Parameter Test conditions
__
Min.
Limits Typ.
VCC = 5.5 V, CE = VIH VCC = 5.5 V, __ CE = VCC 0.2 V __ VCC = 5.5 V, CE = VIL, tRC = 150 ns, IOUT = 0 mA VPP = VPPH VPP = VPPH 0VPPVCC VCCMax. 1 100 15 15 15 10 100 100 30 30 0.2Vcc VCC
Unit mA A mA mA mA A A A mA mA V V V V V V
IOH = -400 A IOH = -100 A
12.0
VCC + 1.0 12.6
AC ELECTRICAL CHARACTERISTICS (Ta = 25 C, VCC = 5 V 10 %, unless otherwise noted) Table 17 Read-only mode Symbol tRC ta(AD) ta(CE) ta(OE) tCLZ tOLZ tDF tDH tWRR Parameter Read cycle time Address access time __ CE access time __ OE access time __ Output enable time (after CE) __ Output enable time (after OE) __ Output floating time (after OE) __ __ Output valid time (after CE, OE, address) Write recovery time (before read) Limits Min. 500 Max. 500 500 200 0 0 70 0 6 Unit ns ns ns ns ns ns ns ns s
Table 18 Read/Write mode Symbol tWC tAS tAH tDS tDH tWRR tRRW tCS tCH tWP tWPH tDP tDE tVSC Write cycle time Address set up time Address hold time Data setup time Data hold time Write recovery time (before read) Read recovery time (before write) __ CE setup time __ CE hold time Write pulse width Write pulse waiting time Program time Erase time VPP setup time Parameter Limits Min. 300 0 120 100 20 6 0 40 0 120 40 10 9.5 1 Max. Unit ns ns ns ns ns s s ns ns ns ns s ms s
Note: Read timing of Read/Write mode is same as Read-only mode.
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FUNCTIONAL DESCRIPTION
(2) Flash memory mode 2 (serial I/O mode)
The M38B79FF has a function to serially input/output the software commands, addresses, and data required for operation on the internal flash memory (e. g., read, program, and erase) using only a few pins. This is called the serial I/O (input/output) mode. This mode can be selected by driving the SDA (serial data input/out__ put), SCLK (serial clock input ), and OE pins high after connecting wires as shown in Figures 91 and powering on the VCC pin and then applying VPPH to the VPP pin. In the serial I/O mode, the user can use six types of software commands: read, program, program verify, erase, erase verify and error check. Serial input/output is accomplished synchronously with the clock, beginning from the LSB (LSB first).
*P27/FLD7 *P26/FLD6 *P25/FLD5 *P24/FLD4 *P23/FLD3 *P22/FLD2 *P21/FLD1 *P20/FLD0 VEE PB6/SIN1 PB5/SOUT1 PB4/SCLK11 PB3/SSTB1 PB2/SBUSY1 PB1/SRDY1 PB0/SCLK12/SVIN/DA AVSS VREF PA7/AN7 PA6/AN6
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
*P00/FLD8 *P01/FLD9 *P02/FLD10 *P03/FLD11 *P04/FLD12 *P05/FLD13 *P06/FLD14 *P07/FLD15 *P10/FLD16 *P11/FLD17 *P12/FLD18 *P13/FLD19 *P14/FLD20 *P15/FLD21 *P16/FLD22 *P17/FLD23 *P30/FLD24 *P31/FLD25 *P32/FLD26 *P33/FLD27 *P34/FLD28 *P35/FLD29 *P36/FLD30 *P37/FLD31 *P40/FLD32 *P41/FLD33 *P42/FLD34 *P43/FLD35 *P44/FLD36 *P45/FLD37
OE
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
M38B79FFFP
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
*P46/FLD38 *P47/FLD39 *P50/FLD40 *P51/FLD41 *P52/FLD42 *P53/FLD43 *P54/FLD44 *P55/FLD45 *P56/FLD46 *P57/FLD47 *P60/FLD48 *P61/FLD49 *P62/FLD50 *P63/FLD51 P64/RxD/FLD52 P65/TxD/FLD53 P66/SCLK21/FLD54 P67/SRDY2/SCLK22/FLD55 P70/INT0 P71/INT1
SDA SCLK BUSY
Vss
Vcc
Fig. 91 Pin connection of M38B79FF when operating in serial I/O mode
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PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 P97/BUZ02/AN15 P96/PWM0/AN14 P95/RTP0/AN13 P94/RTP1/AN12 P93/SRDY3/AN11 P92/SCLK3/AN10 P91/SOUT3/AN9 P90/SIN3/AN8 P83/CNTR0/CNTR2 P82/CNTR1 Vpp CNVSS RESET P81/XCOUT P80/XCIN VSS XIN XOUT VCC P77/INT4/BUZ01 P76/T3OUT P75/T1OUT P74/PWM1 P73/INT3/DIMOUT P72/INT2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
:Connect to the ceramic oscillation circuit.
*: High-breakdown-voltage output port: Totaling 52
Package type: 100P6S-A
indicates the flash memory pin.
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FUNCTIONAL DESCRIPTION
Table 19 Pin description (flash memory serial I/O mode) Pin VCC, VSS CNVSS _____ RESET XIN XOUT AVSS VREF P00-P07 P10-P17 P20-P27 P30-P36 P37 P40-P47 P50-P57 P60-P63, P65 P64 P66 P67 P70-P77 P80-P83 P90-P97 PA0-PA7 PB0-PB6 VEE Name Power supply VPP input Reset input Clock input Clock output Analog supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Control signal input Input port P4 Input port P5 Input port P6 SDA I/O SCLK input BUSY output Input port P7 Input port P8 Input port P9 Input port PA Input port PB Pull-down power supply Input /Output -- Input Input Input Output -- Input Input Input Input Input Input Input Input Input I/O Input Output Input Input Input Input Input Functions Supply 5 V 10 % to VCC and 0 V to VSS. Connect to 11.7 V to 12.6 V. Connect to VSS. Connect a ceramic resonator between XIN and XOUT. Connect to VSS. Input an arbitrary level between the range of VSS and VCC. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. __ OE input pin Input "H" or "L" , or keep them open. Input "H" or "L", or keep them open. Input "H" or "L" to P60-P63, P65, or keep them open. This pin is for serial data I/O. This pin is for serial clock input. This pin is for BUSY signal output. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Keep this open.
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Functional Outline (serial I/O mode)
In the serial I/O mode, data is transferred synchronously with the clock using serial input/output. The input data is read from the SDA pin into the internal circuit synchronously with the rising edge of the serial clock pulse; the output data is output from the SDA pin synchronously with the falling edge of the serial clock pulse. Data is transferred in units of eight bits. In the first transfer, the user inputs the command code. This is followed by address input and data input/output according to the contents of the command. Table 20 shows the software commands used in the serial I/O mode. The following explains each software command.
Table 20 Software command (serial I/O mode) Number of transfers First command Command code input Read 0016 Program 4016 Program verify C016 Erase 2016 Erase verify A016 Error check 8016 Second Read address L (Input) Program address L (Input) Verify data (Output) 2016 (Input) Verify address L (Input) Error code (Output) Third Read address H (Input) Program address H (Input) ---------- ---------- Verify address H (Input) ---------- Fourth Read data (Output) Program data (Input) ---------- ---------- Verify data (Output) ----------
__
q Read command Input command code 0016 in the first transfer. Proceed and input the low-order 8 bits and the high-order 8 bits of the address and __ pull the OE pin low. When this is done, the M38B79FF reads out the contents of the specified address, and then latchs it into the in-
ternal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, the read data that has been latched into the data latch is serially output from the SDA pin.
tCH SCLK A0 SDA A7
tCH
A8
A15
D0
D7
00000000 Command code input (0016) Read address input (L)
Read address input (H) tCR
tWR
tRC
Read data output
OE Read BUSY "L" Note : When outputting the read data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 92 Timings during reading
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FUNCTIONAL DESCRIPTION
q Program command Input command code 4016 in the first transfer. Proceed and input the low-order 8 bits and the high-order 8 bits of the address and then program data. Programming is initiated at the last rising edge of the serial clock during program data transfer. The BUSY pin is driven high during program operation. Programming is completed within 10 s as measured by the internal timer, and the BUSY pin is pulled low. Note : A programming operation is not completed by executing the program command once. Always be sure to execute a program verify command after executing the program command. When the failure is found in the verification, the user must repeatedly execute the program command until the pass in the verification. Refer to Figure 90 for the programming flowchart.
tCH SCLK
tCH
tCH
tPC A0 SDA 00000010 Command code input (4016) A7 A8 A15 D0 D7
Program address input (L) Program address input (H)
Program data input
OE
tWP Program
BUSY
Fig. 93 Timings during programming
__
q Program verify command Input command code C016 in the first transfer. Proceed and drive __ the OE pin low. When this is done, The M38B79FF verify-reads the programmed address's contents, and then latchs it into the in-
ternal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, the verify data that has been latched into the data latch is serially output from the SDA pin.
SCLK D0 SDA 00000011 Command code input (C016) tCRPV OE Verify read BUSY
"L"
D7
Verify data output tWR tRC
Note: When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 94 Timings during program verify
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FUNCTIONAL DESCRIPTION
q Erase command Input command code 2016 in the first transfer and command code 2016 again in the second transfer. When this is done, the M38B79FF executes an erase command. Erase is initiated at the last rising edge of the serial clock. The BUSY pin is driven high during the erase operation. Erase is completed within 9.5 ms as measured by the internal timer, and the BUSY pin is pulled low. Note that data 0016 must be written to all memory locations before executing the erase command. Note: A erase operation is not completed by executing the erase command once. Always be sure to execute a erase verify command after executing the erase command. When the failure is found in the verification, the user must repeatedly execute the erase command until the pass in the verification. Refer to Figure 90 for the erase flowchart.
tCH SCLK tEC SDA 00000100 00000100 Command code input (2016) Command code input (2016) "H" OE twE BUSY Erase
Fig. 95 Timings at erasing
q Erase verify command The user must verify the contents of all addresses after completing the erase command. Input command code A016 in the first transfer. Proceed and input the low-order 8 bits and the high-order __ 8 bits of the address and pull the OE pin low. When this is done, the M38B79FF reads out the contents of the specified __ address, and then latchs it into the internal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, the
verify data that has been latched into the data latch is serially output from the SDA pin. Note: If any memory location where the contents have not been erased is found in the erase verify operation, execute the operation of "erase erase verify" over again. In this case, however, the user does not need to write data 0016 to memory locations before erasing.
tCH SCLK A0 SDA A7
tCH
A8
A15
D0
D7
00000101 Command code input (A016) Verify address input (L)
Verify address input (H) tCREV
tWR
tRC
Verify data output
OE Verify read BUSY "L" Note : When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 96 Timings during erase verify
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FUNCTIONAL DESCRIPTION
q Error check command Input command code 8016 in the first transfer, and the M38B79FF outputs error information from the SDA pin, beginning at the next falling edge of the serial clock. If the LSB bit of the 8-bit error information is 1, it indicates that a command error has occurred. A command error means that some invalid commands other than commands shown in Table 20 has been input. When a command error occurs, the serial communication circuit sets the corresponding flag and stops functioning to avoid an erroneous programming or erase. When being placed in this state, the serial communication circuit does not accept the subsequent serial clock and data (even including an error check command). Therefore, if the user wants to execute an error check command, temporarily drop the VPP pin input to the VPPL level to terminate the serial input/output mode. Then, place the M38B79FF into the serial I/O mode back again. The serial communication circuit is reset by this operation and is ready to accept commands. The error flag alone is not cleared by this operation, so the user can examine the serial communication circuit's error conditions before reset. This examination is done by the first execution of an error check command after the reset. The error flag is cleared when the user has executed the error check command. Because the error flag is undefined immediately after power-on, always be sure to execute the error check command.
tCH SCLK E0 SDA 00000001 Command code input (8016) "H" ??????? Error flag output
OE
BUSY "L"
Note: When outputting the error flag, the SDA pin is switched for output at the first falling edge of the serial clock. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of the serial clock (at the 8th bit).
Fig. 97 Timings at error checking
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DC ELECTRICAL CHARACTERISTICS (Ta = 25 C, VCC = 5 V 10 %, VPP = 11.7 to 12.6 V, unless otherwise noted)
ICC, IPP-relevant standards during read, program, and erase are the same as in the parallel input/output mode. VIH, VIL, VOH, VOL, IIH, and __ IIL for the SCLK, SDA, BUSY, OE pins conform to the microcomputer modes.
Table 21 AC Electrical characteristics (Ta = 25 C, VCC = 5 V 10 %, VPP = 11.7 to 12.6 V, f(XIN) = 4 MHz, unless otherwise noted) Symbol tCH tCR tWR tRC tCRPV tWP tPC tCREV tWE tEC tc(CK) tw(CKH) tw(CKL) tr(CK) tf(CK) td(C-Q) th(C-Q) th(C-E) tsu(D-C) th(C-D) Parameter Serial transmission interval Read waiting time after transmission Read pulse width Transfer waiting time after read Waiting time before program verify Programming time Transfer waiting time after programming Waiting time before erase verify Erase time Transfer waiting time after erase SCLK input cycle time SCLK high-level pulse width SCLK low-level pulse width SCLK rise time SCLK fall time SDA output delay time SDA output hold time SDA output hold time (only the 8th bit) SDA input set up time SDA input hold time Limits Min. 625(Note 1) 625(Note 1) 500(Note 2) 625(Note 1) 6 625(Note 1) 6 9.5 625(Note 1) 250 100 100 20 20 90 0 0 187.5 (Note 3) 312.5(Note 4) 30 90 Max. Unit ns ns ns ns s s ns s ms ns ns ns ns ns ns ns ns ns ns ns
10
Notes 1: When f(XIN) = 4 MHz or less, calculate the minimum value according to formula 1. 2500 x 106 f(XIN) 2: When f(XIN) = 4 MHz or less, calculate the minimum value according to formula 2. Formula 1 : 2000 x 106 f(XIN) 3: When f(XIN) = 4 MHz or less, calculate the minimum value according to formula 3. Formula 2 : 750 x 106 f(XIN) 4: When f(XIN) = 4 MHz or less, calculate the minimum value according to formula 4 Formula 3 : Formula 4 : 1250 f(XIN) x 106
AC waveforms
tf(CK) tw(CKL)
tc(CK) tr(CK)
tw(CKH)
SCLK th(C-Q) td(C-Q) th(C-E) Test conditions for AC characteristics SDA output * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V tsu(D-C) th(C-D) * Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC
SDA input
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FUNCTIONAL DESCRIPTION
(3) Flash memory mode 3 (CPU reprogramming mode)
The M38B79FF has the CPU reprogramming mode where a builtin flash memory is handled by the central processing unit (CPU). In CPU reprogramming mode, the flash memory is handled by writing and reading to/from the flash memory control register (see Figure 98) and the flash command register (see Figure 99). The CNVSS pin is used as the VPP power supply pin in CPU reprogramming mode. It is necessary to apply the power-supply voltage of VPPH from the external to this pin. by checking this flag after each command of erase and the program is executed. Bits 4, 5 of the flash memory control register are the erase/program area select bits. These bits specify an area where erase and program is operated. When the erase command is executed after an area is specified by these bits, only the specified area is erased. Only for the specified area, programming is enabled; for the other areas, programming is disabled. Figure 100 shows the CPU mode register bit configuration in the CPU reprogramming mode.
Functional Outline (CPU reprogramming mode)
Figure 98 shows the flash memory control register bit configuration. Figure 99 shows the flash command register bit configuration. Bit 0 of the flash memory control register is the CPU reprogramming mode select bit. When this bit is set to "1" and VPPH is applied to the CNVss/VPP pin, the CPU reprogramming mode is selected. Whether the CPU reprogramming mode is realized or not is judged by reading the CPU reprogramming mode monitor flag (bit 2 of the flash memory control register). Bit 1 is a busy flag which becomes "1" during erase and program execution. Whether these operations have been completed or not is judged
7
6 0
5
4
3 0
2
1
0 Flash memory control regsiter (FCON : address 0EFE16) CPU reprogramming mode select bit (Note) 0 : CPU reprogramming mode is invalid. (Normal operation mode) 1 : When applying 0 V or VPPL to CNVSS/VPP pin, CPU reprogramming mode is invalid. When applying VPPH to CNVSS/VPP pin, CPU reprogramming mode is valid. Erase/Program busy flag 0 : Erase and program are completed or not have been executed. 1 : Erase/program is being executed. CPU reprogramming mode monitor flag 0 : CPU reprogramming mode is invalid. 1 : CPU reprogramming mode is valid. Fix this bit to "0". Erase/Program area select bits 0 0 : Addresses 100016 to FFFF16 (total 60 Kbytes) 0 1 : Addresses 100016 to 7FFF16 (total 28 Kbytes) 1 0 : Addresses 800016 to FFFF16 (total 32 Kbytes) 1 1 : Not available Fix this bit to "0". Not used (returns "0" when read)
Note: Bit 0 can be reprogrammed only when 0 V is applied to the CNVSS/VPP pin.
Fig. 98 Flash memory control register bit configuration
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FUNCTIONAL DESCRIPTION
q CPU reprogramming mode operation procedure The operation procedure in CPU reprogramming mode is described below. < Beginning procedure > Apply 0 V to the CNVss/VPP pin for reset release. Set the CPU mode register. (see Figure 100) After CPU reprogramming mode control program is transferred to internal RAM, jump to this control program on RAM. (The following operations are controlled by this control program). Set "1" to the CPU reprogramming mode select bit. Apply VPPH to the CNVSS/VPP pin. Wait till CNVSS/VPP pin becomes 12 V. Read the CPU reprogramming mode monitor flag to confirm whether the CPU reprogramming mode is valid. The operation of the flash memory is executed by software-command-writing to the flash command register . Note: The following are necessary other than this: *Control for data which is input from the external (serial I/O etc.) and to be programmed to the flash memory *Initial setting for ports etc. *Writing to the watchdog timer
< Release procedure > Apply 0V to the CNVSS/VPP pin. Wait till CNVSS/VPP pin becomes 0V. Set the CPU reprogramming mode select bit to "0". Each software command is explained as follows. q Read command When "0016" is written to the flash command register, the M38B79FF enters the read mode. The contents of the corresponding address can be read by reading the flash memory (For instance, with the LDA instruction etc.) under this condition. The read mode is maintained until another command code is written to the flash command register. Accordingly, after setting the read mode once, the contents of the flash memory can continuously be read. After reset and after the reset command is executed, the read mode is set.
b7 7 6 5 4 3 2 1 0 Flash command register (FCMD : address 0EFF16) Writing of software command * Read command * Program command * Program verify command * Erase command * Erase verify command * Reset command "0016" "4016" "C016" "2016" + "2016" "A016" "FF16" + "FF16"
b0
0
0
CPU mode register
(CPUM : address 003B16)
Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Not available 1 X : Not available Stack page selection bit 0 : 0 page 1 : 1 page Reserved (Do not write "0" to this bit when using XCIN-XCOUT oscillation function.) Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : = f(XIN) (high-speed mode) 0 1 : = f(XIN)/4 (middle-speed mode) 1 0 : = f(XCIN)/2 (low-speed mode) 1 1 : Not available
Note: The flash command register is write-only register.
Fig. 99 Flash command register bit configuration
Fig. 100 CPU mode register bit configuration in CPU rewriting mode
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FUNCTIONAL DESCRIPTION
q Program command When "4016" is written to the flash command register, the M38B79FF enters the program mode. Subsequently to this, if the instruction (for instance, STA instruction) for writing byte data in the address to be programmed is executed, the control circuit of the flash memory executes the program. The erase/program busy flag of the flash memory control register is set to "1" when the program starts, and becomes "0" when the program is completed. Accordingly, after the write instruction is executed, CPU can recognize the completion of the program by polling this bit. The programmed area must be specified beforehand by the erase/ program area select bits. During programming, watchdog timer stops with "FFFF16" set. Note: A programming operation is not completed by executing the program command once. Always be sure to execute a program verify command after executing the program command. When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer to Figure 101 for the flow chart of the programming. q Program verify command When "C016" is written to the flash command register, the M38B79FF enters the program verify mode. Subsequently to this, if the instruction (for instance, LDA instruction) for reading byte data from the address to be verified (i.e., previously programmed address), the contents which has been written to the address actually is read. CPU compares this read data with data which has been written by the previous program command. In consequence of the comparison, if not agreeing, the operation of "program program verify" must be executed again. q Erase command When writing "2016" twice continuously to the flash command register, the flash memory control circuit performs erase to the area specified beforehand by the erase/program area select bits. Erase/program busy flag of the flash memory control register becomes "1" when erase begins, and it becomes "0" when erase completes. Accordingly, CPU can recognize the completion of erase by polling this bit. Data "0016" must be written to all areas to be erased by the program and the program verify commands before the erase command is executed. During erasing, watchdog timer stops with "FFFF16" set. Note: The erasing operation is not completed by executing the erase command once. Always be sure to execute an erase verify command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 101 for the erasing flowchart. q Erase verify command When "A016" is written to the flash command register, the M38B79FF enters the erase verify mode. Subsequently to this, if the instruction (for instance, LDA instruction) for reading byte data from the address to be verified, the contents of the address is read. CPU must erase and verify to all erased areas in a unit of address. If the address of which data is not "FF16" (i.e., data is not erased) is found, it is necessary to discontinue erasure verification there, and execute the operation of "erase erase verify" again. Note: By executing the operation of "erase erase verify" again when the memory not erased is found. It is unnecessary to write data "0016" before erasing in this case. q Reset command The reset command is a command to discontinue the program or erase command on the way. When "FF16" is written to the command register two times continuously after "4016" or "2016" is written to the flash command register, the program, or erase command becomes invalid (reset), and the M38B79FF enters the reset mode. The contents of the memory does not change even if the reset command is executed.
DC Electric Characteristics
Note: The characteristic concerning the flash memory part are the same as the characteristic of the parallel I/O mode.
AC Electric Characteristics
Note: The characteristics are the same as the characteristic of the microcomputer mode.
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Program START
Erase START
ADRS = first location
YES
ALL BYTES = 0016 ? NO
X=0 WRITE PROGRAM COMMAND WRITE PROGRAM DATA
4016
PROGRAM ALL BYTES = 0016
ADRS = first location DIN X=0
WAIT 1s WRITE ERASE COMMAND NO ERASE PROGRAM BUSY FLAG = 0 YES X=X+1 WRITE PROGRAM-VERIFY COMMAND DURATION = 6 s WRITE ERASE COMMAND 2016
2016
WAIT 1s C016
NO
ERASE PROGRAM BUSY FLAG = 0 YES X=X+1
X = 25 ? NO FAIL
YES WRITE ERASE-VERIFY COMMAND PASS DURATION = 6 s A016
VERIFY BYTE ? PASS
VERIFY BYTE ? FAIL
X = 1000 ? INC ADRS NO LAST ADRS ? NO YES WRITE READ COMMAND 0016 PASS DEVICE PASSED DEVICE FAILED NO INC ADRS LAST ADRS ? YES WRITE READ COMMAND FAIL
YES
PASS VERIFY BYTE ? VERIFY BYTE ? FAIL
0016
DEVICE PASSED
DEVICE FAILED
Fig. 101 Flowchart of program/erase operation at CPU reprogramming mode
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NOTES ON PROGRAMMING
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1." After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
Serial I/O
*Using an external clock When using an external clock, input "H" to the external clock input pin and clear the serial I/O interrupt request bit before executing serial I/O transfer and serial I/O automatic transfer. *Using an internal clock When using an internal clock, set the synchronous clock to the internal clock, then clear the serial I/O interrupt request bit before executing serial I/O transfer and serial I/O automatic transfer.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction.
Automatic Transfer Serial I/O
When using the automatic transfer serial I/O mode of the serial I/ O1, set an automatic transfer interval as the following. Otherwise the serial data might be incorrectly transmitted/received. *Set an automatic transfer interval for each 1-byte data transfer as the following: (1) Not using FLD controller Keep the interval for 5 cycles or more of internal system clock from clock rising of the last bit of 1-byte data. (2) Using FLD controller (a) Not using gradation display Keep the interval for 17 cycles or more of internal system clock from clock rising of the last bit of 1-byte data. (b) Using gradation display Keep the interval for 27 cycles or more of internal system clock from clock rising of the last bit of 1-byte data.
Decimal Calculations
* To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. * In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
* The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register.
A-D Converter
The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) is at least on 250 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion.
Ports
The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The instruction with the addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers.
D-A Converter
The accuracy of the D-A converter becomes rapidly poor under the VCC = 4.0 V or less condition; a supply voltage of VCC 4.0 V is recommended. When a D-A converter is not used, set the value of D-A conversion register to "0016".
Instruction Execution Time
The instruction execution time is obtained by multiplying the period of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The period of the internal clock is half of the XIN period in highspeed mode.
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NOTES ON USAGE/ DATA REQUIRED FOR MASK ORDERS
NOTES ON USAGE Handling of Power Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin), between power source pin (VCC pin) and analog power source input pin (AVSS pin), and between program power source pin (CNVss/VPP) and GND pin for flash memory version when on-board reprogramming is executed. Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F-0.1 F is recommended.
Flash Memory Version
The CNVSS pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVSS pin and VSS pin or VCC pin with 1 to 10 k resistance. The mask ROM version track of CNVSS pin has no operational interference even if it is connected to Vss pin or Vcc pin via a resistor.
Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs
There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and Flash Memory version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with Flash Memory version and then switching to use of Mask ROM version, please perform sufficient evaluations for the commercial samples of Mask ROM version.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: 1.Mask ROM Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies) or in one floppy disk.
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CHAPTER 2 APPLICATION
I/O port Timer Serial I/O FLD controller A-D converter D-A converter PWM Interrupt interval determination function 2.9 Watchdog timer 2.10 Buzzer output circuit 2.11 Reset circuit 2.12 Clock generating circuit 2.13 Flash memory 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8
APPLICATION
2.1 I/O port
2.1 I/O port
This paragraph describes the setting method of I/O port relevant registers, notes etc. 2.1.1 Memory assignment
Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 0EEF16 0EF016 0EF116 Port P3 (P3) Port P3 direction register (P2D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) Port P9 (P9) Port P9 direction register (P9D) Port PA (PA) Port PA direction register (PAD) Port PB (PB) Port PB direction register (PBD) Pull-up control register 3 (PULL3) Pull-up control register 1 (PULL1) Pull-up control register 2 (PULL2) Port P1 (P1) Port P1 direction register (P0D) Port P2 (P2) Port P0 (P0)
Fig. 2.1.1 Memory assignment of I/O port relevant registers
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2.1 I/O port
2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (i = 0 to 7, 9, A) (Pi: addresses 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16, 1216, 1416)
b
0 1 2 3 4 5 6 7
Name
Port Pi0 Port Pi1 Port Pi2 Port Pi3 Port Pi4 Port Pi5 Port Pi6 Port Pi7
Functions
qIn output mode Write * * * * * * * * Port latch Read * * * * * * * * Port latch qIn input mode Write * * * * * * * * Port latch Read * * * * * * * * Value of pin
At reset R W
0 0 0 0 0 0 0 0
Fig. 2.1.2 Structure of port Pi (i = 0 to 7, 9, A)
Port P8
b7 b6 b5 b4 b3 b2 b1 b0 Port P8 (P8: address 1016)
b
Name
Functions
qIn output mode Write * * * * * * * * Port latch Read * * * * * * * * Port latch qIn input mode Write * * * * * * * * Port latch Read * * * * * * * * Value of pin
At reset R W
0 0 0 0 0 0 0 0
0 Port P80 1 Port P81 2 Port P82 3 Port P83
4 Nothing is arranged for these bits. When these 5 bits are read out, the contents are undefined. 6 7
Fig. 2.1.3 Structure of port P8
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APPLICATION
2.1 I/O port Port PB
b7 b6 b5 b4 b3 b2 b1 b0 Port PB (PB: address 1616)
b
0 1 2 3 4 5 6 7
Name
Functions
At reset R W
0 0 0 0 0 0 0 0
Port PB0 qIn output mode Port PB1 Write * * * * * * * * Port latch Port PB2 Read * * * * * * * * Port latch qIn input mode Port PB3 Write * * * * * * * * Port latch Port PB4 Read * * * * * * * * Value of pin Port PB5 Port PB6 Nothing is arranged for this bit. When this bit is read out, the contents are undefined.
Fig. 2.1.4 Structure of port PB
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 1, 3 to 7, 9, A) [Addresses 0316, 0716, 0916, 0B16, 0D16, 0F16, 1316, 1516]
b
Name
Functions
0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode
At reset R W
0 0 0 0 0 0 0 0
0 Port Pi direction register 1 2 3 4 5 6 7
Fig. 2.1.5 Structure of port Pi (i = 1, 3 to 7, 9, A) direction register
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APPLICATION
2.1 I/O port
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port P8 direction register (P8D: address 1116)
b
Name
Functions
At reset R W
0 0 0 0 0 0 0 0
0 Port P8 direction register 1 2 3 4 5 6 7
0 : Port P80 input mode 1 : Port P80 output mode 0 : Port P81 input mode 1 : Port P81 output mode 0 : Port P82 input mode 1 : Port P82 output mode 0 : Port P83 input mode 1 : Port P83 output mode Nothing is arranged for these bits. When these bits are read out, the contents are undefined.
Fig. 2.1.6 Structure of port P8 direction register
Port PB direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port PB direction register (PBD: address 1716)
b
Name
Functions
At reset R W
0 0 0 0 0 0 0 0
0 Port PB direction register 1 2 3 4 5 6 7
0 : Port PB0 input mode 1 : Port PB0 output mode 0 : Port PB1 input mode 1 : Port PB1 output mode 0 : Port PB2 input mode 1 : Port PB2 output mode 0 : Port PB3 input mode 1 : Port PB3 output mode 0 : Port PB4 input mode 1 : Port PB4 output mode 0 : Port PB5 input mode 1 : Port PB5 output mode 0 : Port PB6 input mode 1 : Port PB6 output mode Nothing is arranged for this bit. When this bit is read out, the contents are undefined.
Fig. 2.1.7 Structure of port PB direction register
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APPLICATION
2.1 I/O port
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 1 (PULL1: address 0EF016)
b
Name
Functions
At reset R W
0 0 0 0 0 0 0 0
0: No pull-up 0 Ports P64, P65 1: Pull-up pull-up control 0: No pull-up 1 Ports P66, P67 1: Pull-up pull-up control 0: No pull-up 2 Ports P70, P71 1: Pull-up pull-up control 0: No pull-up 3 Ports P72, P73 pull-up control 1: Pull-up 0: No pull-up 4 Ports P74, P75 pull-up control 1: Pull-up Ports P76, P77 0: No pull-up 5 pull-up control 1: Pull-up 6 Nothing is arranged for these bits. These are write disabled bits. When these bits are read 7 out, the contents are "0".
Note: The pin set to output port is cut off from pull-up control.
Fig. 2.1.8 Structure of pull-up control register 1
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 2 (PULL2: address 0EF116)
b
Name
Functions
At reset R W
0 0 0
0 Ports P80, P81 pull- 0: No pull-up 1: Pull-up up control Ports P82, P83 pull- 0: No pull-up 1 1: Pull-up up control 2 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0". 3 Ports P90, P91 pull- 0: No pull-up up control 1: Pull-up 4 Ports P92, P93 pull- 0: No pull-up 1: Pull-up up control 5 Ports P94, P95 pull- 0: No pull-up 1: Pull-up up control 6 Ports P96, P97 pull- 0: No pull-up up control 1: Pull-up Nothing is arranged for this bit. This is a write 7 disabled bit. When this bit is read out, the contents are "0".
0 0 0 0 0
Note: The pin set to output port is cut off from pull-up control.
Fig. 2.1.9 Structure of pull-up control register 2
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APPLICATION
2.1 I/O port
Pull-up control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 3 (PULL3: address 0EEF16)
b
Name
Functions
0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up
At reset R W
0 0 0 0 0 0 0 0
0 Ports PA0, PA1 pull-up control 1 Ports PA2, PA3 pull-up control 2 Ports PA4, PA5 pull-up control 3 Ports PA6, PA7 pull-up control 4 Ports PB0, PB1 pull-up control 5 Ports PB2, PB3 pull-up control 6 Ports PB4, PB5 pull-up control 7 Ports PB6 pull-up control
Note: The pin set to output port is cut off from pull-up control.
Fig. 2.1.10 Structure of pull-up control register 3
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APPLICATION
2.1 I/O port
2.1.3 Terminate unused pins Table 2.1.1 Termination of unused pins Pins Termination P0, P2 Open at "H" output state. P1, P3-P5, P60- * Set to the input mode and connect each to VCC or VSS through a resistor of 1 k to P63 10 k. * Set to the output mode and open at "H" output state. P64-P67, P7, P80- * Set to the input mode and connect each to VCC or VSS through a resistor of 1 k to P83, P9, PA, PB0- 10 k. PB6 * Set to the output mode and open at "L" or "H" output state. VREF Open. XOUT Open (only when using external clock). AVSS Connect to VSS (GND). VEE Connect to VSS (GND). CNVSS Connect to VSS through a resistor of 1 k to 10 k.
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APPLICATION
2.1 I/O port
2.1.4 Notes on I/O port (1) Notes in standby state In standby state 1 for low-power dissipation, do not make input levels of an input port and an I/O port "undefined". Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, note the following points: * External circuit * Variation of output levels during the ordinary operation When using an optional built-in pull-up resistor, note on varied current values: * When setting as an input port : Fix its input level * When setting as an output port : Prevent current from flowing out to external q Reason The potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an I/O port are "undefined". This may cause power source current. 1 standby state: stop mode by executing STP instruction wait mode by executing WIT instruction (2) Modifying port latch of I/O port with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction 2, the value of the unspecified bit may be changed. q Reason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch. *As for bit which is set for input port: The pin state is read in the CPU, and is written to this bit after bit managing. *As for bit which is set for output port: The bit value is read in the CPU, and is written to this bit after bit managing. Note the following: *Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. *As for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. 2 Bit managing instructions: SEB and CLB instructions (3) Pull-up/Pull-down control When each port which has built-in pull-up/pull-down resistor is set to output port, pull-up/pull-down control of corresponding port becomes invalid. (Pull-up/pull-down cannot be set.) q Reason Pull-up/pull-down control is valid only when each direction register is set to the input mode.
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APPLICATION
2.1 I/O port
2.1.5 Termination of unused pins (1) Terminate unused pins Output ports : Open Input ports : Connect each pin to VCC or VSS through each resistor of 1 k to 10 k. As for pins whose potential affects to operation modes such as pin INT or others, select the VCC pin or the VSS pin according to their operation mode. I/O ports : * Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of 1 k to 10 k. Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/O ports for the output mode and open them at "L" or "H". * When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. * Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) Termination remarks Input ports and I/O ports : Do not open in the input mode. q Reason * The power source current may increase depending on the first-stage circuit. * An effect due to noise may be easily produced as compared with proper termination and shown on the above. I/O ports : When setting for the input mode, do not connect to VCC or VSS directly. q Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and VCC (or VSS). I/O ports : When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through a resistor. q Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. * At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins.
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APPLICATION
2.2 Timer
2.2 Timer
This paragraph explains the registers setting method and the notes relevant to the timers. 2.2.1 Memory map
002016 002116 002216 002316 002416 002516
Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer 5 (T5) Timer 6 (T6)
002616 (PWM control register (PWMCON)) 002716 Timer 6 PWM register (T6PWM) 002816 002916 002A16 Timer 12 mode register (T12M) Timer 34 mode register (T34M) Timer 56 mode register (T56M)
002B16 (D-A conversion register (DA)) 002C16 Timer X (low-order) (TXL) 002D16 002E16 002F16 Timer X (high-order) (TXH) Timer X mode register 1 (TXM1) Timer X mode register 2 (TXM2)
003C16 003D16 003E16 003F16
Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt c ntrol register 1 (ICON1) o Interrupt control register 2 (ICON2)
Fig. 2.2.1 Memory map of registers relevant to timers
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APPLICATION
2.2 Timer
2.2.2 Relevant registers (1) 8-bit timer
Timer i
b7 b6 b5 b4 b3 b2 b1 b0 Timer i (i = 1, 3 to 6) (Ti: addresses 2016, 2216, 2316, 2416, 2516)
b
Functions
At reset R W
1 1 1 1 1 1 1 1
0 * Set timer i count value. 1 * The value set in this register is written to both 2 the timer i and the timer i latch at one time. 3 * When the timer i is read out, the count value 4 of the timer i is read out. 5 6 7
Fig. 2.2.2 Structure of Timer i (i=1, 3 to 6)
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2: address 2116)
b
Functions
At reset R W
1 0 0 0 0 0 0 0
0 * Set timer 2 count value. 1 * The value set in this register is written to both 2 the timer 2 and the timer 2 latch at one time. 3 * When the timer 2 is read out, the count value 4 of the timer 2 is read out. 5 6 7
Fig. 2.2.3 Structure of Timer 2
Timer 6 PWM register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 6 PWM register (T6PWM: address 2716)
b
0 1 2 3 4 5 6 7
Functions
* In timer 6 PWM1 mode "L" level width of PWM rectangular waveform is set. * Duty of PWM rectangular waveform: n/(n + m) Period: (n + m) x ts n = timer 6 set value m = timer 6 PWM register set value ts = timer 6 count source period At n = 0, all PWM output "L". At m = 0, all PWM output "H". (However, n = 0 has priority.) * Selection of timer 6 PWM1 mode Set "1" to the timer 6 operation mode selection bit.
At reset R W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Fig. 2.2.4 Structure of Timer 6 PWM register 2-12
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APPLICATION
2.2 Timer
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 12 mode register (T12M: address 2816)
b
Name
Functions
0: Count operation 1: Count stop 0: Count operation 1: Count stop
b3 b2
At reset R W
0 0 0
0 Timer 1 count stop bit 1 Timer 2 count stop bit 2 Timer 1 count source selection 3 bits 4 Timer 2 count source selection bits 5
0 0: f(XIN)/8 or f(XCIN)/16 0 1: f(XCIN) 1 0: f(XIN)/16 or f(XCIN)/32 1 1: f(XIN)/64 or f(XCIN)/128
b5 b4
0 0: Timer 1 underflow 0 1: f(XCIN) 1 0: External count input CNTR0 1 1: Not available 0: I/O port 6 Timer 1 output selection bit (P75) 1: Timer 1 output 7 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0".
0 0 0 0
Fig. 2.2.5 Structure of Timer 12 mode register
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 34 mode register (T34M: address 2916)
b
Name
Functions
0: Count operation 1: Count stop 0: Count operation 1: Count stop
b3 b2
At reset R W
0 0 0
0 Timer 3 count stop bit 1 Timer 4 count stop bit 2 Timer 3 count source selection 3 bits 4 Timer 4 count source selection bits 5
0 0: f(XIN)/8 or f(XCIN)/16 0 1: Timer 2 underflow 1 0: f(XIN)/16 or f(XCIN)/32 1 1: f(XIN)/64 or f(XCIN)/128
b5 b4
0 0: f(XIN)/8 or f(XCIN)/16 0 1: Timer 3 underflow 1 0: External count input CNTR1 1 1: Not available 0: I/O port 6 Timer 3 output selection bit (P76) 1: Timer 3 output 7 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0".
0 0 0 0
Fig. 2.2.6 Structure of Timer 34 mode register
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APPLICATION
2.2 Timer
Timer 56 mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 56 mode register (T56M: address 2A16)
b
Name
Functions
0: Count operation 1: Count stop 0: Count operation 1: Count stop 0: f(XIN)/8 or f(XCIN)/16 1: Timer 4 underflow 0: Timer mode 1: PWM mode
b5 b4
At reset R W
0 0 0 0 0 0 0
0 Timer 5 count stop bit 1 Timer 6 count stop bit Timer 5 count 2 source selection bit 3 Timer 6 operation mode selection bit 4 Timer 6 count source selection 5 bits 6 Timer 6 (PWM) output selection bit (P74)
0 0: f(XIN)/8 or f(XCIN)/16 0 1: Timer 5 underflow 1 0: Timer 4 underflow 1 1: Not available 0: I/O port 1: Timer 6 output
7 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0".
0
Fig. 2.2.7 Structure of Timer 56 mode register
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APPLICATION
2.2 Timer
(2) 16-bit timer
Timer X (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0 Timer X (low-order, high-order) (TXL, TXH: addresses 2C16, 2D16)
b
Functions
At reset R W
1 1 1 1 1 1 1 1
0 * Set timer X count value. 1 * When the timer X write control bit of the timer X mode register 1 is "0", the value is written to 2 timer X and the latch at one time. 3 When the timer X write control bit of the timer X mode register 1 is "1", the value is written 4 only to the latch. 5 * The timer X count value is read out by reading 6 this register. 7
Notes 1: When reading and writing, perform them to both the highorder and low-order bytes. 2: Read both registers in order of TXH and TXL following. 3: Write both registers in order of TXL and TXH following. 4: Do not read both registers during a write, and do not write to both registers during a read.
Fig. 2.2.8 Structure of Timer X (low-order, high-order)
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APPLICATION
2.2 Timer
Timer X mode register 1
b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register 1 (TXM1: address 2E16)
b
Name
Functions
0 : Write value in latch and counter 1 : Write value in latch only
At reset R W
0
0 Timer X write control bit
b2 b1 1 Timer X count 0 0: f(XIN)/2 or f(XCIN)/4 source selection bits 0 1: f(XIN)/8 or f(XCIN)/16 1 0: f(XIN)/64 or f(XCIN)/128 2 1 1: Not available 3 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0".
0 0 0
4 Timer X operating mode bits 5
b5 b4
0
0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode
0
6 CNTR2 active edge 0 : *Start from "H" output in pulse output mode switch bit *Count at rising edge in event counter mode *Measure "H" pulse width in pulse width measurement mode 1 : *Start from "L" output in pulse output mode *Count at falling edge in event counter mode *Measure "L" pulse width in pulse width measurement mode 7 Timer X stop control bit 0 : Count operating 1 : Count stop
0
0
Fig. 2.2.9 Structure of Timer X mode register 1
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APPLICATION
2.2 Timer
Timer X mode register 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register 2 (TXM2: address 2F16)
b
Name
bit (P94)
Functions
0: Real time port function is invalid 1: Real time port function is valid 0: Real time port function is invalid 1: Real time port function is valid 0: "L" output 1: "H" output 0: "L" output 1: "H" output
At reset R W
0
0 Real time port control
1 Real time port control
bit (P95)
0 0 0 0 0 0 0 0
2 P94 data for real time
port
3 P95 data for real time
port
4 Nothing is arranged for these bits. These are 5 write disabled bits. When these bits are read 6 out, the contents are "0". 7
Fig. 2.2.10 Structure of Timer X mode register 2
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APPLICATION
2.2 Timer
(3) 8-bit timer, 16-bit timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1 : address 3C16)
b
Name
Functions
0 : No interrupt request issued 1 : Interrupt request issued
At reset R W
0
0 INT0 interrupt request bit
1 INT1/serial I/O3 0 : No interrupt request interrupt request bit issued 1 : Interrupt request issued 2 INT2 interrupt 0 : No interrupt request request bit issued Remote controller 1 : Interrupt request issued /counter overflow interrupt request bit 3 Serial I/O1 interrupt 0 : No interrupt request issued request bit Serial I/O automatic 1 : Interrupt request issued transfer interrupt request bit 4 Timer X interrupt request bit 5 Timer 1 interrupt request bit 6 Timer 2 interrupt request bit 7 Timer 3 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued
0
0
0
0
0
0
0
: "0" can be set by software, but "1" cannot be set.
Fig. 2.2.11 Structure of Interrupt request register 1
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APPLICATION
2.2 Timer
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2 : address 3D16)
b
Name
Functions
At reset R W
0 0 0 0 0
0 : No interrupt request issued 0 Timer 4 interrupt 1 : Interrupt request issued request bit 0 : No interrupt request issued 1 Timer 5 interrupt 1 : Interrupt request issued request bit Timer 6 interrupt 0 : No interrupt request issued 2 1 : Interrupt request issued request bit 3 Serial I/O2 receive 0 : No interrupt request issued interrupt request bit 1 : Interrupt request issued 0 : No interrupt request issued 4 INT3/Serial I/O2 1 : Interrupt request issued transmit interrupt request bit 0 : No interrupt request issued 5 INT4 interrupt 1 : Interrupt request issued request bit A-D converter interrupt request bit 0 : No interrupt request issued 6 FLD blanking interrupt request bit 1 : Interrupt request issued FLD digit interrupt request bit 7 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are "0". : "0" can be set by software, but "1" cannot be set.
0
0
0
Fig. 2.2.12 Structure of Interrupt request register 2
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APPLICATION
2.2 Timer Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1 : address 3E16)
b
Name
Functions
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset R W
0 0 0
0 INT0 interrupt enable bit 1 INT1/serial I/O3 interrupt enable bit 2 INT2 interrupt enable bit Remote controller /counter overflow interrupt enable bit 3 Serial I/O1 interrupt enable bit Serial I/O automatic transfer interrupt enable bit Timer X interrupt 4 enable bit 5 Timer 1 interrupt enable bit 6 Timer 2 interrupt enable bit 7 Timer 3 interrupt enable bit
0 : Interrupt disabled 1 : Interrupt enabled
0
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
0 0 0 0
Fig. 2.2.13 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2 : address 3F16)
b
Name
Functions
0 : interrupt disabled 1 : Interrupt enabled 0 : interrupt disabled 1 : Interrupt enabled 0 : interrupt disabled 1 : Interrupt enabled 0 : interrupt disabled 1 : Interrupt enabled 0 : interrupt disabled 1 : Interrupt enabled 0 : interrupt disabled 1 : Interrupt enabled
At reset R W
0 0 0 0 0
0 Timer 4 interrupt enable bit 1 Timer 5 interrupt enable bit Timer 6 interrupt 2 enable bit 3 Serial I/O2 receive interrupt enable bit 4 INT3/Serial I/O2 transmit interrupt enable bit 5 INT4 interrupt enable bit A-D converter interrupt enable bit 6 FLD blanking interrupt enable bit FLD digit interrupt enable bit 7 Fix "0" to this bit.
0
0 : interrupt disabled 1 : Interrupt enabled
0
0
Fig. 2.2.14 Structure of Interrupt control register 2 2-20
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APPLICATION
2.2 Timer
2.2.3 Timer application examples (1) Basic functions and uses [Function 1] Control of event interval (Timer 1 to Timer 6, Timer X: timer mode) When a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs. |
